Trench with reduced silicon loss

Abstract

An isolation trench in a substrate of a semiconductor device includes a first shallow portion, a transition region, and a second deeper portion. The isolation trench contains a dielectric filler. The isolation trench is formed by first forming a first shallow portion of the isolation trench, forming polysilicon sidewalls on the first shallow portion, and then etching the second deeper portion.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a substrate;   an isolation trench in said substrate having a shallower portion and a deeper portion and a transition region between said deeper portion and said shallower portion, wherein a first slope of a first sidewall of said transition region sidewall is less vertical than a second slope of a second sidewall of said shallower portion and is less vertical than a third slope of a third sidewall of said deeper portion and said second slope is less vertical than said third slope, said isolation trench containing a dielectric fill material.   
     
     
         2 . The semiconductor device of  claim 1  wherein a depth of said shallow portion is in the range of 100 to 500 nm. 
     
     
         3 . The semiconductor device of  claim 1  wherein a depth of said deeper portion is in the range of 100 nm to 500 nm. 
     
     
         4 . The semiconductor device of  claim 1  wherein a depth of said isolation trench is in the range of 200 nm to 1000 nm. 
     
     
         5 . A semiconductor device, comprising:
 a substrate;   an isolation trench in said substrate having a shallower portion and a deeper portion and a transition region between said deeper portion and said shallower portion, wherein a first slope of a first sidewall of said shallower portion and is less vertical than a second slope of a second sidewall of said deeper portion, said isolation trench containing a dielectric fill material.   
     
     
         6 . The semiconductor device of  claim 5  wherein a depth of said shallow portion is in the range of 100 to 500 nm. 
     
     
         7 . The semiconductor device of  claim 5  wherein a depth of said deeper portion is in the range of 100 nm to 500 nm. 
     
     
         8 . The semiconductor device of  claim 5  wherein a depth of said isolation trench is in the range of 200 nm to 1000 nm.