Non-volatile memory structure and manufacturing method thereof

Abstract

A method for manufacturing a non-volatile memory structure includes providing a substrate having a gate structure, performing a first oxidation process to form a first SiO layer at least covering a bottom corner of the conductive layer, performing a first etching process to remove the first SiO layer and a portion of the dielectric layer to form a cavity, performing a second oxidation process to form a second SiO layer covering sidewalls of the cavity and a third SiO layer covering a surface of the substrate, forming a first SiN layer filling in the cavity and covering the gate structure on the substrate, and removing a portion of the first SiN layer to form a SiN structure including a foot portion filling in the cavity and an erection portion upwardly extended from the foot portion, and the erection portion covering sidewalls of the gate structure.

1 . A method for manufacturing a non-volatile memory structure, comprising:
 providing a substrate having a gate structure formed thereon, the gate structure comprising a conductive layer and a dielectric layer;   performing a first oxidation process to form a first silicon oxide (SiO) layer at least covering a bottom corner of the conductive layer;   performing a first etching process to remove the first SiO layer and a portion of the dielectric layer to form a cavity under the conductive layer;   performing a second oxidation process to form a second SiO layer covering sidewalls of the cavity and a third SiO layer covering a surface of the substrate;   forming a first silicon nitride (SiN) layer on the substrate, the first SiN layer filling in the cavity and covering the gate structure; and   removing a portion of the first SiN layer to form a SiN structure comprising a foot portion filling in the cavity and an erection portion upwardly extended from the foot portion, and the erection portion covering sidewalls of the gate structure.   
     
     
         2 . The method for manufacturing the non-volatile memory structure according to  claim 1 , further comprising performing a second etching process to remove a portion of the dielectric layer to form a recess in the dielectric layer before the first oxidation process. 
     
     
         3 . The method for manufacturing the non-volatile memory structure according to  claim 2 , wherein the cavity is larger than the recess. 
     
     
         4 . The method for manufacturing the non-volatile memory structure according to  claim 1 , further comprising forming lightly-doped drains (LDDs) in the substrate after forming the SiN structure. 
     
     
         5 . The method for manufacturing the non-volatile memory structure according to  claim 1 , further comprising forming a spacer on the sidewalls of the gate structure, and the spacer is in contact with the SiN structure. 
     
     
         6 . The method for manufacturing the non-volatile memory structure according to  claim 5 , wherein the spacer further comprises a fourth SiO layer and a second SiN layer, and the fourth SiO layer is sandwiched between the SiN structure and the second SiN layer. 
     
     
         7 . The method for manufacturing the non-volatile memory structure according to  claim 1 , further comprising forming a source/drain in the substrate at two sides of the gate structure. 
     
     
         8 . The method for manufacturing the non-volatile memory structure according to  claim 1 , wherein the second SiO layer, the foot portion of the SiN structure, and the third SiO layer construct an oxide-nitride-oxide (ONO) structure. 
     
     
         9 . A non-volatile memory structure comprising:
 a substrate;   a gate structure formed on the substrate, the gate structure comprising a conductive layer and a dielectric layer;   a cavity formed in a portion of the dielectric layer of the gate structure and a portion of a bottom of the conductive layer of the gate structure;   a SiN structure formed on sidewalls of the gate structure, the SiN structure comprising:
 a foot portion formed in between the gate structure and the substrate, the foot portion inwardly extended into the gate structure, and the cavity being filled with the foot portion; and 
 an erection portion upwardly extended from the foot portion, the erection portion covering the sidewalls of the gate structure; and 
   lightly doped drains (LDDs) formed in the substrate, the LDDs being not overlapped with the SiN structure.   
     
     
         10 . The non-volatile memory structure according to  claim 9 , wherein a width of the dielectric layer is smaller than a width of the conductive layer. 
     
     
         11 . The non-volatile memory structure according to  claim 9 , further comprising a first SiO layer covering a bottom of the conductive layer and a second SiO layer covering a surface of the substrate under the gate structure. 
     
     
         12 . The non-volatile memory structure according to  claim 11 , wherein the first SiO layer, the foot portion of the SiN structure, and the second SiO layer construct an ONO structure. 
     
     
         13 . The non-volatile memory structure according to  claim 9 , further comprising a spacer covering the erection portion of the SiN structure. 
     
     
         14 . The non-volatile memory structure according to  claim 13 , wherein the spacer further comprises a third SiO layer and a SiN layer, and the third SiO layer is sandwiched between the SiN layer and the erection portion of the SiN structure. 
     
     
         15 . The non-volatile memory structure according to  claim 9 , further comprising a source/drain formed in the substrate.