Thin film transistor array panel and manufacturing method thereof

Abstract

A thin film transistor array panel includes a substrate, an insulation layer, a first semiconductor, and a second semiconductor. The insulation layer is disposed on the substrate and includes a stepped portion. The first semiconductor is disposed on the insulation layer. The second semiconductor is disposed on the insulation layer and includes a semiconductor material different than the first semiconductor. The stepped portion is spaced apart from an edge of the first semiconductor.

What is claimed is: 
     
         1 . A method of manufacturing a thin film transistor array panel, comprising:
 forming a first insulation layer on a substrate;   forming a first semiconductor material layer on the first insulation layer;   forming an etching passivation material layer on the first semiconductor material layer;   forming a first photoresist layer on the etching passivation material layer;   etching, using the first photoresist layer as a mask, the etching passivation material layer to form an etching passivation layer;   etching, using the first photoresist layer as a mask, the first semiconductor material layer to form a first semiconductor pattern comprising a protrusion not covered by the etching passivation layer;   forming, sequentially, a second insulation layer and a second semiconductor material layer on the etching passivation layer and the first semiconductor pattern;   forming a second photoresist layer on the second semiconductor material layer;   etching, using the second photoresist layer as a mask, the second semiconductor material layer to form a first semiconductor;   etching the first insulation layer not covered by the second photoresist layer and the protrusion not covered by the etching passivation layer to form a second semiconductor comprising an undercut region under the etching passivation layer; and   forming, in the first insulation layer, a stepped portion spaced apart from an edge of the second semiconductor.   
     
     
         2 . The method of  claim 1 , wherein:
 the stepped portion of the first insulation layer faces an edge of the etching passivation layer.   
     
     
         3 . The method of  claim 2 , wherein:
 etching ratios of the second insulation layer and the first semiconductor pattern are substantially the same.   
     
     
         4 . The method of  claim 3 , wherein:
 at least one of an angle between a side surface of the edge of the second semiconductor and a surface of the substrate and an angle between a side surface of the stepped portion and the surface of the substrate is larger than approximately 90 degrees and smaller than approximately 180 degrees.   
     
     
         5 . The method of  claim 4 , wherein:
 etching the first semiconductor material layer to form the first semiconductor comprises leaving a portion of the first semiconductor material layer at a portion not covered by the second photoresist layer, the left portion forming a residual semiconductor material layer; and   the residual semiconductor material layer is simultaneously etched in association with etching the first insulation layer and the protrusion.   
     
     
         6 . The method of  claim 5 , wherein:
 an etching gas used in association with etching the first insulation layer and the protrusion comprises sulfur hexafluoride gas (SF 6 ) and oxygen gas (O 2 ).   
     
     
         7 . The method of  claim 6 , wherein:
 the second semiconductor material layer comprises amorphous silicon.   
     
     
         8 . The method of  claim 7 , wherein:
 the first semiconductor material layer comprises silicon germanium.   
     
     
         9 . The method of  claim 8 , further comprising:
 removing the second photoresist layer and the etching passivation layer after forming the second semiconductor and the stepped portion of the first insulation layer; and   forming an electrode on the first semiconductor and the second semiconductor.   
     
     
         10 . The method of  claim 9 , wherein:
 the electrode comprises an electrode covering the edge of the second semiconductor and the stepped portion.   
     
     
         11 . The method of  claim 1 , wherein:
 etching ratios of the first insulation layer and the first semiconductor pattern are substantially the same.   
     
     
         12 . The method of  claim 1 , wherein:
 at least one of an angle between a side surface of the edge of the second semiconductor and a surface of the substrate and an angle between a side surface of the stepped portion and the surface of the substrate is larger than approximately 90 degrees and smaller than approximately 180 degrees.   
     
     
         13 . The method of  claim 1 , wherein:
 etching the first semiconductor material layer to form the first semiconductor comprises leaving a portion of the first semiconductor material layer at a portion not covered by the second photoresist layer, the left portion forming a residual semiconductor material layer; and   the residual semiconductor material layer is simultaneously etched in association with etching the first insulation layer and the protrusion.   
     
     
         14 . A thin film transistor array panel, comprising:
 a substrate;   an insulation layer disposed on the substrate, the insulation layer comprising a stepped portion;   a first semiconductor disposed on the insulation layer; and   a second semiconductor disposed on the insulation layer, the second semiconductor comprising a semiconductor material different than the first semiconductor,   wherein the stepped portion is spaced apart from an edge of the first semiconductor.   
     
     
         15 . The thin film transistor array panel of  claim 14 , further comprising:
 an insulator disposed between the second semiconductor and the insulation layer.   
     
     
         16 . The thin film transistor array panel of  claim 15 , wherein:
 the first semiconductor and the insulator comprise dry etched surfaces.   
     
     
         17 . The thin film transistor array panel of  claim 16 , wherein:
 at least one of an angle between a side surface of the edge of the first semiconductor and a surface of the substrate and an angle between a side surface of the stepped portion and the surface of the substrate is larger than approximately 90 degrees and smaller than approximately 180 degrees.   
     
     
         18 . The thin film transistor array panel of  claim 17 , wherein:
 the first semiconductor comprises amorphous silicon.   
     
     
         19 . The thin film transistor array panel of  claim 18 , wherein:
 the second semiconductor comprises silicon germanium.   
     
     
         20 . The thin film transistor array panel of  claim 19 , further comprising:
 an electrode disposed on the edge of the first semiconductor.   
     
     
         21 . The thin film transistor array panel of  claim 20 , wherein:
 the electrode covers the stepped portion.   
     
     
         22 . The thin film transistor array panel of  claim 14 , wherein:
 the first semiconductor forms a portion of a first thin-film transistor;   the second semiconductor forms a portion of a second thin film transistor; and   an output of the first thin-film transistor is electrically connected to an input of the second thin-film transistor.   
     
     
         23 . The thin film transistor array panel of  claim 22 , wherein the second thin film transistor comprises a visible light sensing transistor or an infrared light sensing transistor.