Power supply device

Abstract

Miniaturization of a multiphase type power supply device can be achieved. A power supply control unit in which, for example, a microcontroller unit, a memory unit and an analog controller unit are formed over a single chip, a plurality of PWM-equipped drive units, and a plurality of inductors configure a multiphase power supply. The microcontroller unit outputs clock signals each having a frequency and a phase defined based on a program on the memory unit to the respective PWM-equipped drive units. The analog controller unit detects a difference between a voltage value of a load and a target voltage value acquired via a serial interface and outputs an error amp signal therefrom. Each of the PWM-equipped drive units drives each inductor by a peak current control system using the clock signal and the error amp signal.

What is claimed is: 
     
         1 . A power supply device comprising:
 a plurality of drive units, each of which is provided in a first semiconductor package and includes:   a high-side transistor and a low-side transistor coupled each other, the high-side and low-side transistors being adapted to be coupled with an inductor which couples with an output power supply node;   a current detection circuit for detecting a current flowing through the high-side transistor;   a pulse width modulation (PWM) control circuit generating a PWM signal which controls the high-side and low-side transistors; and   a control unit provided in a second semiconductor package,
 the control unit providing a clock signal and an error amp signal for each of the plurality of drive units, 
 the PWM signal being controlled based on the error amp signal, and 
 the error amp signal being generated based on a voltage level of the output power supply node. 
   
     
     
         2 . A power supply device according to  claim 1 ,
 wherein the output power supply node is adapted to be coupled with a load.   
     
     
         3 . A power supply device according to  claim 2 ,
 wherein the load is a CPU, a GPU or a memory.   
     
     
         4 . A power supply device according to  claim 1 ,
 wherein the first and second semiconductor packages are mounted over a circuit board.   
     
     
         5 . A power supply device according to  claim 1 ,
 wherein a peak value of a current flowing through the inductor is controlled based on the error amp signal.   
     
     
         6 . A power supply device according to  claim 1 ,
 wherein the control unit includes a microcontroller unit and an analog controller unit,   wherein the microcontroller unit provides the clock signal to each of the plurality of drive units via the analog controller unit, and   wherein the analog controller unit includes an error amplifier which generates the error amp signal.   
     
     
         7 . A power supply device according to  claim 6 ,
 wherein the control unit includes a memory unit storing a program.   
     
     
         8 . A power supply device comprising:
 a plurality of first drive units and a second drive unit each of which is provided in a first semiconductor package and includes:   a high-side transistor and a low-side transistor coupled each other,
 the high-side and low-side transistors of the plurality of the first drive units being adapted to be coupled with a first inductor which couples with a first output power supply node, and 
 the high-side and low-side transistors of the second drive unit being adapted to be coupled with a second inductor which couples with a second output power supply node; 
   a current detection circuit for detecting a current flowing through the high-side transistor;   a pulse width modulation (PWM) control circuit generating a PWM signal which controls the high-side and low-side transistors; and   a control unit provided in a second semiconductor package,
 the control unit providing a first clock signal and a first error amp signal for each of the plurality of the first drive units, the PWM signal generated in each of the plurality of first drive units being controlled based on the first error amp signal, and 
 the control unit providing a second clock signal and a second error amp signal for the second drive unit, the PWM signal generated in the second drive unit being controlled based on the second error amp signal. 
   
     
     
         9 . A power supply device according to  claim 8 ,
 wherein the first and second output power supply nodes are adapted to be coupled with a load.   
     
     
         10 . A power supply device according to  claim 9 ,
 wherein the load is a CPU, a GPU or a memory.   
     
     
         11 . A power supply device according to  claim 8 ,
 wherein the first and second semiconductor packages are mounted over a circuit board.   
     
     
         12 . A power supply device according to  claim 8 ,
 wherein a peak value of a current flowing through the first inductor is controlled based on the first error amp signal, and   wherein a peak value of a current flowing through the second inductor is controlled based on the second error amp signal.   
     
     
         13 . A power supply device according to  claim 8 ,
 wherein the control unit includes a microcontroller unit and an analog controller unit,   wherein the microcontroller unit provides the first and second clock signals to each of the plurality of the first drive units and the second drive unit via the analog controller unit, and   wherein the analog controller unit includes an first error amplifier and a second error amplifier which generate the first error amp signal and the second error amp signal, respectively.   
     
     
         14 . A power supply device according to  claim 13 ,
 wherein the control unit includes a memory unit storing a program.