Processor configured for operation with multiple operation codes per instruction

Abstract

A method of associating operation codes with instructions for execution in a processor includes the steps of assigning the operation codes to the instructions in a manner that allows a given instruction to have multiple assigned operation codes and selecting a particular one of the multiple assigned operation codes for use in executing a program containing the given instruction. The assigning step may be implemented in conjunction with design of the processor, and may further comprise the steps of determining frequency of occurrence of adjacent pairs of instructions in one or more programs likely to be run on the processor, and assigning the operation codes to the instructions based at least in part on the determined frequency of occurrence of the adjacent pairs of instructions. The selecting step may be implemented in conjunction with code generation for the program containing the given instruction, for example, in a code assembler.

What is claimed is: 
     
         1 . A method of associating operation codes with instructions for execution in a processor, the method comprising the steps of:
 assigning the operation codes to the instructions in a manner that allows a given instruction to have multiple assigned operation codes; and   selecting a particular one of the multiple assigned operation codes for use in executing a program containing the given instruction.   
     
     
         2 . The method of  claim 1  wherein the assigning step is implemented in conjunction with design of the processor. 
     
     
         3 . The method of  claim 1  wherein the assigning step is implemented on a data processing device used to design the processor. 
     
     
         4 . The method of  claim 1  wherein the assigning step further comprises the steps of:
 determining frequency of occurrence of adjacent pairs of instructions in one or more programs likely to be run on the processor; and 
 assigning the operation codes to the instructions based at least in part on the determined frequency of occurrence of the adjacent pairs of instructions. 
 
     
     
         5 . The method of  claim 1  wherein the method further comprises the step of designing the processor, the designing step comprising designing processing circuitry of the processor to decode a first operation code to produce the given instruction and to decode a second operation code different than the first operation code to also produce the given instruction, that same instruction thereby being produced for execution by the processing circuitry regardless of whether the first operation code or the second operation code is decoded. 
     
     
         6 . The method of  claim 5  further including the step of manufacturing the processor comprising the processing circuitry. 
     
     
         7 . The method of  claim 1  wherein the selecting step is implemented in conjunction with code generation for the program containing the given instruction. 
     
     
         8 . The method of  claim 1  wherein the selecting step is implemented in a code assembler. 
     
     
         9 . The method of  claim 1  further including the step of executing the assembled code of the program using the selected operation code. 
     
     
         10 . A system for associating operation codes with instructions for execution in a processor, the system comprising:
 a data processing device configured to permit assignment of the operation codes to the instructions in a manner that allows a given one of the instructions to have multiple assigned operation codes; and   a code assembler configured to select a particular one of the multiple assigned operation codes for inclusion in assembled code of a program containing the given instruction.   
     
     
         11 . The system of  claim 10  wherein the data processing device comprises a computer. 
     
     
         12 . The system of  claim 11  wherein the code assembler is implemented within the computer. 
     
     
         13 . The system of  claim 11  wherein the code assembler is implemented on a processing platform separate from the computer. 
     
     
         14 . A data processing device for associating operation codes with instructions for execution in a processor, the data processing device being configured to assign the operation codes to the instructions in a manner that allows a given instruction to have multiple assigned operation codes, wherein a particular one of the multiple assigned operation codes is selected for use in executing a program containing the given instruction. 
     
     
         15 . A code assembler configured for use with operation codes associated with instructions for execution in a processor, the operation codes being assigned to the instructions in a manner that allows a given instruction to have multiple assigned operation codes, wherein the code assembler is configured to select a particular one of the multiple assigned operation codes for use by the processor in executing a program containing the given instruction.