Clock Synchronization In A Memory System

Abstract

Synchronization is provided in a memory system. During memory write operations a timing reference signal is transmitted with control signals to a memory device, and a calibration signal is received from the memory device. An internal clock signal is adjusted based on the calibration signal, and a data signal is then transmitted according to the internal clock. In this manner, the data is synchronized such that the data is accurately sampled according to the local clock signal.

What is claimed is: 
     
         1 . An integrated circuit device comprising:
 a first interface configured to transmit, to a dynamic random access memory (DRAM):
 a clock signal, 
 control signals including first and second control signals, the first control signals encoding a write command to indicate that write data be written to the DRAM, the second control signals encoding a read command to indicate that read data be output from the DRAM, the control signals being registered by the DRAM at one or more edges of the clock signal, and 
 a timing reference signal, the write data being registered by the DRAM at one or more edges of the timing reference signal, and 
 the first interface to receive, from the DRAM, a write calibration signal that indicates a phase difference between the clock signal and the timing reference signal; and 
   a second interface configured to transmit the write data associated with the write command and sample the read output from the DRAM, wherein the write data is transmitted using a first internal clock signal having a phase offset that is set based on the received write calibration signal, and the read data is sampled using a second internal clock signal having a phase offset based on a transmitted pattern received from the DRAM.