Semiconductor device and fabrication method thereof

Abstract

A semiconductor device includes a gate electrode formed on a sidewall of a structure extending from a semiconductor substrate. A junction region is form in the structure to a first depth from a top of the structure and formed to overlap the gate electrode. A protection layer is formed between an outer wall of the structure and the gate electrode to a second depth less than the first depth from the top of the structure.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a gate electrode formed on a sidewall of a structure extending from a semiconductor substrate;   a junction region formed in the structure to a first depth from a top of the structure and formed to overlap the gate electrode; and   a protection layer formed between an outer wall of the structure and the gate electrode to a second depth less than the first depth from the top of the structure.   
     
     
         2 . The semiconductor device of  claim 1 , further comprising:
 a gate insulating layer formed between the junction region and is the gate electrode and between the protection layer and the gate electrode.   
     
     
         3 . The semiconductor device of  claim 2 , wherein the protection layer is made of a material having a dielectric constant that is lower than a dielectric constant of the gate insulating layer. 
     
     
         4 . The semiconductor device of  claim 2 , wherein the protection layer has an oxidation rate that is greater than an oxidation rate of the semiconductor substrate. 
     
     
         5 . A semiconductor device, comprising:
 a first junction region;   a gate electrode formed in the first junction region;   a channel region formed on the first junction region and extending along the gate electrode to a certain height, wherein the channel region is electrically connected to the first junction region;   a second junction region formed on the channel region and extending along the gate electrode to a certain height, wherein the second junction region is electrically connected to the channel region; and   a protection layer formed between the gate electrode and the second junction region, in a region where the gate electrode and the second junction region overlap.   
     
     
         6 . The semiconductor device of  claim 5 , wherein the first junction region is a common source region. 
     
     
         7 . A semiconductor device, comprising:
 a gate electrode formed in a trench formed in a semiconductor substrate;   junction regions formed at both sides of the gate electrode; and   a protection layer formed in the trench between the gate electrode and each of the junction regions, in a region where the gate electrode and each of the junction regions overlap.   
     
     
         8 . A method of fabricating a semiconductor device, the method comprising:
 patterning a semiconductor substrate to form preliminary pillars;   forming a protection layer on each of the preliminary pillars;   patterning the semiconductor substrate between the preliminary pillars to form pillar structures;   forming a gate electrode on a sidewall of each of the pillar structures; and   implanting an impurity into each of the pillar structures to a depth that is greater than a height of each of the preliminary pillars.   
     
     
         9 . The method of  claim 8 , wherein the protection layer is formed of a material having an oxidation rate that is greater than an oxidation rate of the semiconductor substrate. 
     
     
         10 . The method of  claim 8 , further comprising:
 implanting an impurity into the semiconductor substrate to form a common source region that will be electrically connected to the pillar structure.   
     
     
         11 . The method of  claim 8 , further comprising:
 forming a gate insulating layer on the semiconductor substrate, including the pillar structures,   wherein the protection layer is formed of a material having a dielectric constant that is lower than a dielectric constant of the gate insulating layer.   
     
     
         12 . A method of abricating a semiconductor device, the method comprising:
 patterning a semiconductor substrate to form a preliminary trench;   forming a protection layer in the preliminary trench;   patterning the preliminary trench to form a trench in the semiconductor substrate;   forming, to a certain depth, a gate electrode in the trench; and   implanting an impurity into the semiconductor substrate to a depth that is greater than a depth of the preliminary trench.   
     
     
         13 . The method of  claim 12 , wherein the protection layer is formed of a material having an oxidation rate that is larger than an oxidation rate of the semiconductor substrate. 
     
     
         14 . The method of  claim 12 , further comprising:
 forming a gate insulating layer on the semiconductor substrate, including the trench,   
       wherein the protection layer is formed of a material having a dielectric constant lower that is lower than a dielectric constant of the gate insulating layer.