Use Disposable Gate Cap to Form Transistors, and Split Gate Charge Trapping Memory Cells

Abstract

A semiconductor device and method of making such device is presented herein. The method includes disposing a gate layer over a dielectric layer on a substrate and further disposing a cap layer over the gate layer. A first transistor gate is defined having an initial thickness substantially equal to a combined thickness of the cap layer and the gate layer. A first doped region is formed in the substrate adjacent to the first transistor gate. The cap layer is subsequently removed and a second transistor gate is defined having a thickness substantially equal to the thickness of the gate layer. Afterwards, a second doped region is formed in the substrate adjacent to the second transistor gate. The first doped region extends deeper in the substrate than the second doped region, and a final thickness of the first transistor gate is substantially equal to the thickness of the second transistor gate.

What is claimed is: 
     
         1 . A method of fabricating a semiconductor device, comprising:
 disposing a gate layer over a dielectric on a substrate;   disposing a cap layer over the gate layer;   etching through the cap layer and the gate layer to define a first transistor gate having an initial thickness substantially equal to a combined thickness of the cap layer and the gate layer;   forming a first doped region in the substrate adjacent to the first transistor gate;   removing the cap layer;   etching through the gate layer to define a second transistor gate having a thickness substantially equal to the thickness of the gate layer; and   forming a second doped region in the substrate adjacent to the second transistor gate,   wherein the first doped region extends deeper in the substrate than the second doped region, and a final thickness of the first transistor gate is substantially equal to the thickness of the second transistor gate.   
     
     
         2 . The method of  claim 1 , further comprising forming the dielectric on the substrate before disposing the gate layer, wherein the dielectric has a first thickness in a first region associated with the first transistor gate and a second thickness in a second region associated with the second transistor gate. 
     
     
         3 . The method of  claim 2 , wherein the first thickness is greater than the second thickness. 
     
     
         4 . The method of  claim 1 , wherein disposing a gate layer comprises disposing a polysilicon layer. 
     
     
         5 . The method of  claim 1 , wherein disposing a cap layer comprises disposing a silicon nitride layer. 
     
     
         6 . The method of  claim 1 , wherein forming the first doped region comprises implanting impurities into the substrate using ion implantation. 
     
     
         7 . The method of  claim 6 , wherein the impurities are implanted so as not to penetrate through the combined thickness of the cap layer and the gate layer. 
     
     
         8 . The method of  claim 1 , wherein disposing a cap layer comprises disposing one or more layers. 
     
     
         9 . The method of  claim 8 , wherein disposing one or more layers comprises disposing silicon nitride or silicon dioxide. 
     
     
         10 . The method of  claim 1 , further comprising forming silicide over at least a top surface of the first transistor gate and a top surface of the second transistor gate. 
     
     
         11 . A semiconductor device, comprising:
 a first transistor formed in a substrate, comprising:
 a first transistor gate having a first thickness and a first gate length, and 
 a first doped region in the substrate adjacent to the first transistor gate; and 
   a second transistor formed in the substrate, comprising:
 a second transistor gate having a second thickness substantially equal to the first thickness and a second gate length less than half the length of the first gate length, and 
 a second doped region in the substrate adjacent to the second transistor gate, wherein the first doped region extends deeper in the substrate than the second doped region. 
   
     
     
         12 . The semiconductor device of  claim 11 , wherein the first transistor further comprises a first gate dielectric having a first dielectric thickness, and the second transistor further comprises a second gate dielectric having a second dielectric thickness, the first dielectric thickness being greater than the second dielectric thickness. 
     
     
         13 . The semiconductor device of  claim 12 , wherein the second gate length is about 15-40 nm. 
     
     
         14 . The semiconductor device of  claim 13 , wherein the first gate length is at least 90 nm. 
     
     
         15 . The semiconductor device of  claim 11 , wherein the first transistor further comprises a layer of silicide on a top surface of the first transistor gate and the second transistor further comprises a layer of silicide on a top surface of the second transistor gate. 
     
     
         16 . A method of fabricating a semiconductor device having a first, second, and third region on a substrate, comprising:
 disposing a gate layer over a first dielectric on the substrate;   disposing a cap layer over the gate layer;   forming a plurality of memory cells in the first region, each of the memory cells comprising:
 a select gate disposed over the first dielectric, 
 a memory gate disposed over a second dielectric and adjacent to a sidewall of the select gate, and 
 a first doped region in the substrate adjacent to one side of the select gate and a second doped region in the substrate adjacent to the opposite side of the memory gate; 
   etching through the cap layer and the gate layer in the second region to define a first transistor gate having an initial thickness substantially equal to a thickness of the cap layer and the gate layer;   forming a third doped region in the substrate adjacent to the first transistor gate;   removing the cap layer;   etching through the gate layer in the third region to define a second transistor gate having a thickness substantially equal to the thickness of the gate layer; and   forming a fourth doped region in the substrate adjacent to the second transistor gate, wherein the third doped region extends deeper in the substrate than the fourth doped region, and wherein a final thickness of the first transistor gate is substantially equal to the thickness of the second transistor gate.   
     
     
         17 . The method of  claim 16 , wherein forming a plurality of memory cells comprises:
 etching through the cap layer and the gate layer in the first region to define the select gate disposed over the first dielectric;   disposing the second dielectric over the select gate and the substrate in at least the first region;   disposing a second gate layer over the second dielectric;   etching the second gate layer to define the memory gate disposed over the second dielectric and adjacent to the sidewall of the select gate; and   forming the first and second doped regions in the substrate.   
     
     
         18 . The method of  claim 17 , wherein disposing the second dielectric comprises disposing one or more dielectric layers. 
     
     
         19 . The method of  claim 18 , wherein disposing one or more dielectric layers comprises sequentially disposing oxide, nitride, and oxide (ONO) layers. 
     
     
         20 . The method of  claim 17 , wherein disposing the second gate layer comprises disposing a layer of polysilicon. 
     
     
         21 . The method of  claim 17 , wherein etching the second gate layer comprises performing an etch-back process to define the memory gate that is self-aligned adjacent to the sidewall of the select gate. 
     
     
         22 . The method of  claim 16 , further comprising forming the first dielectric on the substrate before disposing the gate layer, wherein the first dielectric has a first thickness in the second region associated with the first transistor gate and a second thickness in the third region associated with the second transistor gate. 
     
     
         23 . The method of  claim 22 , wherein the first thickness is greater than the second thickness. 
     
     
         24 . The method of  claim 16 , wherein disposing a gate layer comprises disposing a polysilicon layer. 
     
     
         25 . The method of  claim 16 , wherein disposing a cap layer comprises disposing a silicon nitride layer. 
     
     
         26 . The method of  claim 16 , wherein forming the third doped region comprises implanting impurities into the substrate using ion implantation. 
     
     
         27 . The method of  claim 26 , wherein the impurities are implanted so as not to penetrate through the combined thickness of the cap layer and the gate layer. 
     
     
         28 . The method of  claim 16 , wherein disposing a cap layer comprises disposing one or more layers. 
     
     
         29 . The method of  claim 28 , wherein disposing one or more layers comprises disposing silicon nitride or silicon dioxide. 
     
     
         30 . The method of  claim 16 , further comprising forming silicide over at least a top surface of the first transistor gate, the second transistor gate, the select gate, and the memory gate. 
     
     
         31 . A semiconductor device having a first, second, and third region on a substrate, comprising:
 a plurality of memory cells in the first region of the substrate, each of the memory cells comprising:
 a select gate disposed over a first dielectric, 
 a memory gate disposed over a second dielectric and adjacent to a sidewall of the select gate, and 
 a first doped region in the substrate adjacent to one side of the select gate and a second doped region in the substrate adjacent to an opposite side of the memory gate; 
   a plurality of first transistors formed in the second region of the substrate, each of the first transistors comprising:
 a first transistor gate having a first thickness and a first gate length, and 
 a third doped region in the substrate adjacent to the first transistor gate; and 
   a plurality of second transistors formed in the third region of the substrate, each of the second transistors comprising:
 a second transistor gate having a second thickness substantially equal to the first thickness and a second gate length less than half the length of the first gate length, and 
 a fourth doped region in the substrate adjacent to the second transistor gate, wherein the third doped region extends deeper in the substrate than the fourth doped region. 
   
     
     
         32 . The semiconductor device of  claim 31 , wherein a thickness of the memory gate is greater than a thickness of the select gate. 
     
     
         33 . The semiconductor device of  claim 31 , wherein a thickness of the select gate is greater than a thickness of the memory gate. 
     
     
         34 . The semiconductor device of  claim 31 , wherein at least one of the first and second dielectrics comprises one or more dielectric layers. 
     
     
         35 . The semiconductor device of  claim 34 , wherein the one or more dielectric layers comprises a stack of oxide, nitride, and oxide (ONO) layers. 
     
     
         36 . The semiconductor device of  claim 31 , wherein at least one of the select gate and the memory gate is polysilicon. 
     
     
         37 . The semiconductor device of  claim 31 , wherein each of the first transistors further comprises a first gate dielectric having a first dielectric thickness and each of the second transistors further comprises a second gate dielectric having a second dielectric thickness, the first dielectric thickness being greater than the second dielectric thickness. 
     
     
         38 . The semiconductor device of  claim 37 , wherein the second gate length is about 15-40 nm. 
     
     
         39 . The semiconductor device of  claim 38 , wherein the first gate length is at least 90 nm. 
     
     
         40 . The semiconductor device of  claim 31 , further comprising a layer of silicide on a top surface of the memory gate, the select gate, the first transistor gate, and the second transistor gate. 
     
     
         41 . A method of fabricating a semiconductor device having a first, second, and third region on a substrate, comprising:
 disposing a first dielectric on the substrate;   disposing a gate layer over the first dielectric;   disposing a cap layer over the gate layer;   forming a plurality of memory cells in the first region, each of the memory cells comprising:   a memory gate disposed over the first dielectric,   a select gate disposed over a second dielectric and adjacent to a sidewall of the memory gate, and   a first doped region in the substrate adjacent to one side of the select gate and a second doped region in the substrate adjacent to the opposite side of the memory gate;   etching through the cap layer and the gate layer in the second region to define a first transistor gate having an initial thickness substantially equal to a thickness of the cap layer and the gate layer;   forming a third doped region in the substrate adjacent to the first transistor gate;   removing the cap layer;   etching through the gate layer in the third region to define a second transistor gate having a thickness substantially equal to the thickness of the gate layer; and   forming a fourth doped region in the substrate adjacent to the second transistor gate, wherein the third doped region extends deeper in the substrate than the fourth doped region, and wherein a final thickness of the first transistor gate is substantially equal to the thickness of the second transistor gate.   
     
     
         42 . The method of  claim 41 , wherein disposing the first dielectric comprises disposing one or more dielectric layers. 
     
     
         43 . The method of  claim 42 , wherein disposing one or more dielectric layers comprises sequentially disposing oxide, nitride, and oxide (ONO) layers. 
     
     
         44 . The method of  claim 43 , wherein disposing the nitride layer comprises disposing a silicon-rich nitride layer. 
     
     
         45 . The method of  claim 41 , wherein forming a plurality of memory cells comprises:
 etching through the cap layer and the gate layer in the first region to define the memory gate disposed over the first dielectric;   disposing the second dielectric over the memory gate and the substrate in at least the first region;   disposing a second gate layer over the second dielectric;   etching the second gate layer to define the select gate disposed over the second dielectric and adjacent to the sidewall of the memory gate; and   forming the first and second doped regions in the substrate.   
     
     
         46 . The method of  claim 45 , wherein disposing the second gate layer comprises disposing a layer of polysilicon. 
     
     
         47 . The method of  claim 45 , wherein etching the second gate layer comprises performing an etch-back process to define the select gate that is self-aligned adjacent to the sidewall of the memory gate. 
     
     
         48 . The method of  claim 45 , wherein disposing the second dielectric comprises disposing one or more dielectric layers.