Display device, array substrate and manufacturing method thereof

Abstract

A display device, an array substrate and a manufacturing method thereof are provided. The array substrate comprises a substrate, a gate electrode on the substrate, a gate insulating layer, an active layer, an etch stop layer, a source/drain electrode layer, a passivation layer and a pixel electrode layer; wherein the active layer is a metal oxide semiconductor, a metal oxide insulating layer is provided between the gate insulating layer and the active layer, the gate insulating layer is located between the gate electrode and the metal oxide insulating layer, and the metal oxide insulating layer is located between the gate insulating layer and the active layer.

What is claimed is: 
     
         1 . An array substrate, comprising:
 a substrate; a gate electrode, a gate insulating layer, an active layer, an etch stop layer, a source/drain electrode layer, a passivation layer and a pixel electrode layer on the substrate; wherein,   the active layer is a metal oxide semiconductor,   a metal oxide insulating layer is provided between the gate insulating layer and the active layer,   the gate insulating layer is located between the gate electrode and the metal oxide insulating layer, and the metal oxide insulating layer is located between the gate insulating layer and the active layer.   
     
     
         2 . The array substrate according to  claim 1 , wherein, the metal oxide insulating layer has an area larger than or equal to that of the active layer. 
     
     
         3 . The array substrate according to  claim 1 , wherein, the metal oxide insulating layer contacts the active layer. 
     
     
         4 . The array substrate according to  claim 1 , wherein, the gate electrode is copper or copper alloy. 
     
     
         5 . The array substrate according to  claim 1 , wherein, the metal oxide insulating layer is an aluminum oxide (Al 2 O 3 ) thin film, a tantalum pentoxide (Ta 2 O 5 ) thin film or a yttrium oxide (Y 2 O 3 ) thin film. 
     
     
         6 . The array substrate according to  claim 1 , wherein, the etch stop layer is one of, or a composite structure of at least two of a silicon oxide thin film, a silicon nitride thin film and a silicon oxynitride thin film. 
     
     
         7 . The array substrate according to  claim 1 , wherein, the metal oxide insulating layer has a thickness of 50-2000 Å. 
     
     
         8 . A display device comprising the array substrate according to  claim 1 . 
     
     
         9 . A manufacturing method of an array substrate, comprising:
 Step 1, depositing a gate metal film on the substrate, and forming a pattern of a gate electrode through one patterning process;   Step 2, continuously forming thin films comprising a gate insulating layer, a metal oxide insulating layer and a metal oxide semiconductor layer on the substrate after step 1, and forming a pattern of the metal oxide insulating layer and a pattern of the metal oxide semiconductor layer through a pattering process.   
     
     
         10 . The method according to  claim 9 , wherein, the step 2 comprises continuously forming on the substrate after the step 1 thin films comprising the gate insulating layer, the metal oxide insulating layer, the metal oxide semiconductor layer and an etch stop layer, and forming the pattern of the metal oxide insulating layer, the pattern of the metal oxide semiconductor layer, an pattern of the etch stop layer pattern and a contact area pattern of a source/drain electrode and the pattern of the metal oxide semiconductor layer through one half-tone or grey tone mask plate with a plurality of etching processes. 
     
     
         11 . The method according to  claim 9 , further comprising:
 Step 3, forming a source/drain metal film on the substrate after the step 2, and forming a pattern comprising a source electrode, a drain electrode and a date line through one patterning process;   Step 4, forming a passivation layer on the substrate after the step 3, and forming a source electrode contact through hole through one patterning process; and   Step 5, depositing a transparent conductive layer on the substrate after the step 4, and forming a transparent conductive pixel electrode through one patterning process.   
     
     
         12 . The method according to  claim 9 , wherein,
 the step 2 comprises:   Step 211, continuously depositing the gate insulating layer by a PECVD method;   Step 212, continuously and sequentially depositing the metal oxide insulating layer and the metal oxide semiconductor layer on the gate insulating layer by a sputtering or thermal evaporation method;   Step 213, depositing the etch stop layer by the PECVD method;   Step 214, after exposure and development via the one half-tone or gray tone mask plate, forming a photoresist-completely-retained area, a photoresist-completely-removed area and a photoresist-partially-removed area; the photoresist-completely-retained area corresponding to a semiconductor protection portion, the photoresist-partially-removed area corresponding to the contact portion of the source/drain electrodes and the semiconductor layer; and removing the etch stop layer and the semiconductor layer in the photoresist-partially-removed area by an etching process;   Step 215, conducting an aching process of a photoresist to remove the photoresist in the photoresist-partially-removed area; and   Step 216, conducting an etching process, removing the etch stop layer in the photoresist-partially-removed area to form the contact portion of the source/drain electrodes and the semiconductor layer.   
     
     
         13 . The method according to  claim 9 , wherein, the metal oxide insulating layer has an area larger than or equal to that of the metal oxide semiconductor layer. 
     
     
         14 . The method according to  claim 9 , wherein, the metal oxide insulating layer is an aluminum oxide (Al 2 O 3 ) thin film, a tantalum pentoxide (Ta 2 O 5 ) thin film or a yttrium oxide (Y 2 O 3 ) thin film. 
     
     
         15 . The method according to  claim 9 , wherein, the metal oxide insulating layer has a thickness of 50-2000 Å.