Cryptographic information association to memory regions

Abstract

Embodiments herein relate to cryptographic operations, such as encrypting and/or decrypting information to read from or written to first and second memory regions. The first cryptographic information is related to the first memory region and the second cryptographic information is related to the second memory region.

We claim: 
     
         1 . A device comprising:
 a cryptographic module to store first cryptographic information related to at least one of encrypting and decrypting information to be at least one of written to and read from a first memory region and to store second cryptographic information related to at least one of encrypting and decrypting information to be at least one of written to and read from a second memory region; and   an encryptor to,
 at least one of encrypt and decrypt information to be at least one of read from and written to the first memory region based on the first cryptographic information, and 
 at least one of encrypt and decrypt information to be at least one of read from and written to the second memory region based on the second cryptographic information. 
   
     
     
         2 . The device of  claim 1 , wherein,
 the first and second cryptographic information include at least one of algorithm, mode and key information,   the algorithm information includes at least one of a symmetric and asymmetric key algorithm,   the mode information includes at least one a block and stream cipher mode, and   the key information includes at least one of a key value and a reference to a key value.   
     
     
         3 . The device of  claim 2 , wherein,
 a type of at least one of the algorithm, mode, and key information of at least one of the first and second cryptographic information is based on at least one of a source of the information and a type of a memory associated with at least one of the first and second memory regions, and   the type of at least one of the algorithm, mode, and key information of the first cryptographic information is independent from that of the second cryptographic information.   
     
     
         4 . The device of  claim 3 , wherein at least one of the algorithm, mode, and key information of the first cryptographic information related to encrypting the information is different than that of the first cryptographic information related to decrypting the information. 
     
     
         5 . The device of  claim 1 , further comprising:
 a memory management unit (MMU) storing access information related to controlling access to the first and second memory regions; and   a first controller to control access to the first memory region based on the access information, wherein   the access information and the first cryptographic information are provided such that the encryptor and the first controller operate simultaneously.   
     
     
         6 . The device of  claim 5 , further comprising:
 a second controller to control access to the second memory region based on the access information, wherein   the access information and at the second cryptographic information are provided such that the encryptor and the second controller operate simultaneously.   
     
     
         7 . The device of  claim 6 , wherein,
 the encryptor is to transmit information between a processor and at least one of the first and second memory regions,   the encryptor is to at least one of receive information from and transmit information to the first memory region via the first controller, and   the encryptor is to at least one of receive information from and transmit information to the second memory region via the second controller.   
     
     
         8 . The device of  claim 7 , wherein
 the first and second memory regions are external to the device, and   the MMU includes the cryptographic module, the MMU to receive memory access requests from the processor and to map a physical address received from the processor to a virtual address of at least one of the first and second memory regions.   
     
     
         9 . The device of  claim 1 , wherein,
 the encryptor is to at least one of decrypt and pass through the information to be read from at least one of the first and second memory regions based on at least one of the first and second cryptographic information,   the encryptor is to at least one of encrypt and pass through the information to be written to at least one of the first and second memory regions based on at least one of the first and second cryptographic information, and   the encryptor is to operate independently of the processor.   
     
     
         10 . A cryptographic method, comprising:
 receiving a memory access request associated with a first memory region of a plurality of memory regions;   accessing first cryptographic information of a plurality of cryptographic information related to at least one of encrypting information to be written to and decrypting information to be read from the first memory region, each of the plurality of cryptographic information associated with one of the plurality of memory regions; and   at least one of encrypting information to be written to the first memory region based on the first cryptographic information and decrypting information to be read from the first memory region based on the first cryptographic information.   
     
     
         11 . The method of  claim 10 , further comprising:
 receiving a memory access request associated with a second memory region of the plurality of memory regions;   accessing second cryptographic information of a plurality of cryptographic information related to at least one of encrypting information to be written to and decrypting information to be read from the second memory region; and   at least one of encrypting information to be written to the second memory region based on the second cryptographic information and decrypting information to be read from the first memory region based on the second cryptographic information.   
     
     
         12 . The method of  claim 11 , wherein,
 the first and second cryptographic information include at least one of algorithm, mode and key information,   the algorithm information includes at least one of a symmetric and asymmetric key algorithm,   the mode information includes at least one a block and stream cipher mode, and   the key information includes at least one of a value of and a reference to a key.   
     
     
         13 . The method of  claim 12 , wherein,
 a type of at least one of the algorithm, mode, and key information of at least one of the first and second cryptographic information is based on at least one of a source of the information and a type of a memory associated with at least one of the first and second memory regions, and   the type of at least one of the algorithm, mode, and key information of the first cryptographic information is independent from that of the second cryptographic information.   
     
     
         14 . A non-transitory computer-readable storage medium storing instructions that, if executed by a processor of a device, cause the processor to:
 access at least one of first and second cryptographic information, the first cryptographic information related to at least one of encrypting and decrypting information to be at least one of be read from and written to a first memory region, the second cryptographic information related to at least one of encrypting and decrypting information to be at least one of read from and written to a second memory region;   encrypt information to be at least one of written to and read from at least one of the first and second memory regions if at least one of the first and second cryptographic information includes instructions to encrypt the information; and   decrypt information to be at least one of written to and read from at least one of the first and second memory regions if at least one of the first and second cryptographic information includes instructions to decrypt the information, wherein   at least one of an algorithm, mode and key of the first and second cryptographic information is different.   
     
     
         15 . The non-transitory computer-readable storage medium of  claim 14 , further comprising instructions that, if executed by the processor, cause the processor to:
 control access to the first and second memory regions based on access information separate from the first and second cryptographic information, wherein   the access is controlled to occur simultaneously with at least one of the encryption and decryption of the information, and   the first cryptographic information is independent of the second cryptographic information.