US2014159824A1PendingUtilityA1

Orthogonally referenced integrated ensemble for navigation and timing

Assignee: UT BATTELLE LLCPriority: Apr 8, 2011Filed: Feb 13, 2014Published: Jun 12, 2014
Est. expiryApr 8, 2031(~4.7 yrs left)· nominal 20-yr term from priority
G01C 21/10G01S 1/045H03K 3/01H03B 5/30H03B 5/364G01P 15/18H03L 5/00H03L 7/00G01P 15/097H03L 1/028H03B 27/00
53
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

An orthogonally referenced integrated ensemble for navigation and timing includes a dual-polyhedral oscillator array, including an outer sensing array of oscillators and an inner clock array of oscillators situated inside the outer sensing array. The outer sensing array includes a first pair of sensing oscillators situated along a first axis of the outer sensing array, a second pair of sensing oscillators situated along a second axis of the outer sensing array, and a third pair of sensing oscillators situated along a third axis of the outer sensing array. The inner clock array of oscillators includes a first pair of clock oscillators situated along a first axis of the inner clock array, a second pair of clock oscillators situated along a second axis of the inner clock array, and a third pair of clock oscillators situated along a third axis of the inner clock array.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A multi-mode oscillator, comprising:
 a crystal operable to oscillate in a main mode, in a secondary mode and in a tertiary mode, the crystal further operable to output an oscillation signal;   a first circuit operable to separate a main signal of the main mode from the oscillation signal;   a second circuit operable to separate a secondary signal of the secondary mode from the oscillation signal;   a third circuit operable to separate a third signal of the tertiary mode from the oscillation signal; and   a signal processor coupled to the first circuit, the second circuit and the third circuit, the signal processor configured to:
 generate a first output signal based on the main signal and the secondary signal in response to the secondary mode being stable, and 
 generate a second output signal based on the main signal and the tertiary signal in response to the secondary mode being unstable or unreliable. 
   
     
     
         2 . The multi-mode oscillator of  claim 1 , wherein the main mode comprises a third-overtone C mode, the secondary mode comprises a third-overtone B mode, and the tertiary mode comprises a fundamental C mode. 
     
     
         3 . The multi-mode oscillator of  claim 1 , wherein the main mode comprises a third-overtone C mode, the secondary mode comprises a third-overtone B mode, and the tertiary mode comprises a fifth-overtone B mode. 
     
     
         4 . The multi-mode oscillator according to  claim 1 , wherein the crystal comprises a doubly-rotated stress-compensated cut crystal. 
     
     
         5 . The dual-mode oscillator according to  claim 1 , wherein the crystal comprises a doubly rotated IT-cut crystal. 
     
     
         6 . An electronic automatic oscillator gain-control (AGC) circuit comprising a balanced bridge network operable to regulate circuit gain, wherein the balanced bridge network comprises a single-ended gain-control device operable to regulate the circuit gain while maintaining approximate balance in the balanced bridge network. 
     
     
         7 . The electronic AGC circuit of  claim 6 , wherein the single-ended gain-control device comprises a junction gate field-effect transistor (JFET). 
     
     
         8 . The electronic AGC circuit of  claim 6 , further comprising an electronically adjustable differential attenuator, the electronically adjustable differential attenuator configured to exhibit noise contributions from only one device. 
     
     
         9 . The electronic AGC circuit of  claim 6 , further comprising an electronically variable differential attenuator, the electronically variable differential attenuator including only linear circuit elements. 
     
     
         10 . The electronic AGC circuit of  claim 6 , further comprising an electronically variable differential attenuator, the electronically variable differential attenuator configured to exhibit noise contributions from only one active device and fixed resistors.

Join the waitlist — get patent alerts

Track US2014159824A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.