Field effect transistor and method of fabricating the same

Abstract

A field effect transistor is provided. The field effect transistor may include a capping layer on a substrate, a source ohmic electrode and a drain ohmic electrode on the capping layer, a first insulating layer and a second insulating layer stacked on the capping layer to cover the source and drain ohmic electrodes, a Γ-shaped gate electrode including a leg portion and a head portion, the leg portion being connected to the substrate between the source ohmic electrode and the drain ohmic electrode, and the head portion extending from the leg portion to cover a top surface of the second insulating layer, a first planarization layer on the second insulating layer to cover the Γ-shaped gate electrode, and a first electrode on the first planarization layer, the first electrode being connected to the source ohmic electrode or the drain ohmic electrode.

What is claimed is: 
     
         1 . A field effect transistor, comprising:
 a capping layer disposed on a substrate;   a source ohmic electrode and a drain ohmic electrode disposed, spaced apart from each other, on the capping layer;   a first insulating layer and a second insulating layer sequentially stacked on the capping layer to cover the source and drain ohmic electrodes;   a Γ-shaped gate electrode including a leg portion and a head portion, the leg portion being connected to the substrate between the source ohmic electrode and the drain ohmic electrode through the second insulating layer, the first insulating layer and the capping layer, and the head portion extending from the leg portion to cover a top surface of the second insulating layer;   a first planarization layer provided on the second insulating layer to cover the Γ-shaped gate electrode; and   a first electrode provided on the first planarization layer and connected to the source ohmic electrode or the drain ohmic electrode through the first planarization layer, the second insulating layer, and the first insulating layer.   
     
     
         2 . The field effect transistor of  claim 1 , wherein the capping layer defines an undercut region formed adjacent to the leg portion of the Γ-shaped gate electrode. 
     
     
         3 . The field effect transistor of  claim 1 , wherein the capping layer comprises undoped gallium nitride. 
     
     
         4 . The field effect transistor of  claim 1 , wherein the leg portion of the Γ-shaped gate electrode has a section shaped like a letter ‘Y’. 
     
     
         5 . The field effect transistor of  claim 1 , wherein the substrate comprises a silicon carbide substrate, an aluminum nitride buffer layer, an undoped gallium nitride channel layer, an undoped aluminum gallium nitride spacer layer, and an undoped aluminum gallium nitride Schottky layer that are sequentially stacked. 
     
     
         6 . The field effect transistor of  claim 1 , wherein the first insulating layer comprises alumina, and the second insulating layer comprises silicon nitride. 
     
     
         7 . The field effect transistor of  claim 1 , wherein the first planarization layer comprises benzocyclobutene. 
     
     
         8 . The field effect transistor of  claim 1 , further comprising:
 at least one second planarization layer provided on the first planarization layer to cover the first electrode; and   a second electrode provided on the second planarization layer and connected to the first electrode through the second planarization layer.   
     
     
         9 . The field effect transistor of  claim 8 , further comprising a protection layer provided on the second planarization layer to cover the second electrode. 
     
     
         10 . A method of fabricating a field effect transistor, comprising:
 forming a capping layer on a substrate;   forming a source ohmic electrode and a drain ohmic electrode on the capping layer to be spaced apart from each other;   sequentially forming a first insulating layer and a second insulating layer on the capping layer to cover the source and drain electrodes;   forming a photoresist layer with a first opening exposing a portion of the second insulating layer between the source and drain ohmic electrodes;   partially etching the second and first insulating layers using the photoresist layer as an etch mask to define a second opening;   removing the photoresist layer;   partially etching the capping layer using the first and second insulating layers defining the second opening as an etch mask to form a third opening partially exposing the substrate;   forming a Γ-shaped gate electrode with a leg portion connected to the substrate through the third opening and a head portion covering a top surface of the second insulating layer;   forming a first planarization layer on the second insulating layer to cover the Γ-shaped gate electrode; and   forming a first electrode on the first planarization layer, the first electrode being connected to the source ohmic electrode or the drain ohmic electrode through the first planarization layer, the second insulating layer, and the first insulating layer.   
     
     
         11 . The method of  claim 10 , wherein the capping layer is formed of undoped gallium nitride. 
     
     
         12 . The method of  claim 10 , wherein the first insulating layer is formed of alumina and the second insulating layer is formed of silicon nitride. 
     
     
         13 . The method of  claim 10 , wherein the defining of the second opening comprises:
 partially etching the second and first insulating layers using the photoresist layer as an etch mask to form a preliminary second opening having substantially the same width as that of the first opening; and   selectively etching the second insulating layer to define a Y-shaped second opening.   
     
     
         14 . The method of  claim 10 , wherein the defining of the third opening comprises etching a portion of the capping layer using the first and second insulating layers with the second opening as an etch mask, and
 the capping layer is formed to define an undercut region, whose width is greater than that of the first opening.   
     
     
         15 . The method of  claim 14 , wherein the leg portion of the Γ-shaped gate electrode is formed spaced apart from the capping layer, and thereby the third opening is not filled with the leg portion. 
     
     
         16 . The method of  claim 10 , wherein the substrate is a stack of a silicon carbide substrate, an aluminum nitride buffer layer, an undoped gallium nitride channel layer, an undoped aluminum gallium nitride spacer layer, and an undoped aluminum gallium nitride Schottky layer that are sequentially stacked. 
     
     
         17 . The method of  claim 10 , wherein the first planarization layer is formed of benzocyclobutene. 
     
     
         18 . The method of  claim 10 , wherein the forming of the Γ-shaped gate electrode comprises:
 forming a photoresist mold layer on the second insulating layer to define a fourth opening, whose width is greater than those of the first to third openings; 
 forming conductive layers in the third and fourth openings and on the photoresist mold layer; and 
 removing the photoresist mold layer and the conductive layer on the photoresist mold layer. 
 
     
     
         19 . The method of  claim 10 , further comprising:
 forming at least one second planarization layer on the first planarization layer to cover the first electrode; and   forming a second electrode on the second planarization layer, the second electrode being connected to the first electrode through the second planarization layer.   
     
     
         20 . The method of  claim 19 , further comprising, forming a protection layer on the second planarization layer to cover the second electrode.