US2014157220A1PendingUtilityA1

Layout design apparatus and layout design method

Assignee: ARAYAMA MASASHIPriority: Aug 4, 2011Filed: Feb 7, 2014Published: Jun 5, 2014
Est. expiryAug 4, 2031(~5 yrs left)· nominal 20-yr term from priority
G06F 30/394G06F 30/392G06F 17/5072
49
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Claims

Abstract

A layout design apparatus includes: a memory unit to store design data of a hierarchical layout of a multilayer circuit including a macro; a channel count calculation unit to calculate a channel count of channels available to lead wiring from a terminal of the macro to a wiring layer based on the design data stored in the memory unit; and a path calculation unit to calculate a path for leading wiring from a terminal of the macro to the wiring layer in ascending order of the channel count.

Claims

exact text as granted — not AI-modified
1 . (canceled) 
     
     
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         7 . A layout design method, comprising:
 executing by a computer operations of:   calculating a channel count of channels available to lead wiring from a terminal of a macro to a wiring layer based on design data of a hierarchical layout of a multilayer circuit including the macro; and   sequentially calculating a path for leading wiring from a terminal of the macro to the wiring layer in ascending order of the channel count.   
     
     
         8 . The layout design method according to  claim 7 , further comprising,
 determining whether or not a leading path is calculated for all terminals of the macro.   
     
     
         9 . The layout design method according to  claim 7 , further comprising:
 storing information regarding leading paths in the memory unit when the leading path is calculated for all terminals of the macro; and   designing leading wiring for each terminal of the macro based on the information.   
     
     
         10 . The layout design method according to  claim 7 , further comprising:
 calculating a reduction ratio of the channel count for channels available to lead wiring to the wiring layer due to effects from leading wiring of other terminals; and   calculating the path based on a first terminal which reduction ratio is larger than a threshold value and a second terminal that affects the reduction in the channel count of the first terminal.   
     
     
         11 . The layout design method according to  claim 7 , further comprising, going back to a path calculation of a previous terminal before the terminal whose path is not calculated. 
     
     
         12 . The layout design method according to  claim 7 , further comprising, performing the path calculation until a new path other than a calculated path is obtained. 
     
     
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         18 . (canceled)

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