US2014157220A1PendingUtilityA1
Layout design apparatus and layout design method
Est. expiryAug 4, 2031(~5 yrs left)· nominal 20-yr term from priority
G06F 30/394G06F 30/392G06F 17/5072
49
PatentIndex Score
0
Cited by
0
References
0
Claims
Abstract
A layout design apparatus includes: a memory unit to store design data of a hierarchical layout of a multilayer circuit including a macro; a channel count calculation unit to calculate a channel count of channels available to lead wiring from a terminal of the macro to a wiring layer based on the design data stored in the memory unit; and a path calculation unit to calculate a path for leading wiring from a terminal of the macro to the wiring layer in ascending order of the channel count.
Claims
exact text as granted — not AI-modified1 . (canceled)
2 . (canceled)
3 . (canceled)
4 . (canceled)
5 . (canceled)
6 . (canceled)
7 . A layout design method, comprising:
executing by a computer operations of: calculating a channel count of channels available to lead wiring from a terminal of a macro to a wiring layer based on design data of a hierarchical layout of a multilayer circuit including the macro; and sequentially calculating a path for leading wiring from a terminal of the macro to the wiring layer in ascending order of the channel count.
8 . The layout design method according to claim 7 , further comprising,
determining whether or not a leading path is calculated for all terminals of the macro.
9 . The layout design method according to claim 7 , further comprising:
storing information regarding leading paths in the memory unit when the leading path is calculated for all terminals of the macro; and designing leading wiring for each terminal of the macro based on the information.
10 . The layout design method according to claim 7 , further comprising:
calculating a reduction ratio of the channel count for channels available to lead wiring to the wiring layer due to effects from leading wiring of other terminals; and calculating the path based on a first terminal which reduction ratio is larger than a threshold value and a second terminal that affects the reduction in the channel count of the first terminal.
11 . The layout design method according to claim 7 , further comprising, going back to a path calculation of a previous terminal before the terminal whose path is not calculated.
12 . The layout design method according to claim 7 , further comprising, performing the path calculation until a new path other than a calculated path is obtained.
13 . (canceled)
14 . (canceled)
15 . (canceled)
16 . (canceled)
17 . (canceled)
18 . (canceled)Join the waitlist — get patent alerts
Track US2014157220A1 — get alerts on status changes and closely related new filings.
We store only your email — no account needed. See our privacy policy.