US2014157043A1PendingUtilityA1

Memories utilizing hybrid error correcting code techniques

28
Individually held — no corporate assignee on recordPriority: Mar 30, 2012Filed: Mar 30, 2012Published: Jun 5, 2014
Est. expiryMar 30, 2032(~5.7 yrs left)· nominal 20-yr term from priority
Inventors:Joshua Ruggiero
G06F 11/1048G11C 2029/0411G06F 11/1666
28
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

Use of hybrid error correcting code (ECC) techniques. A memory access request having an associated address is received. A memory controller determines whether the address corresponds to a first region of a memory for which ECC techniques are applied or a second region of the memory for which ECC techniques are not applied. The memory access is processed utilizing ECC techniques if the address corresponds to the first region of the memory and processed without utilizing the ECC techniques if the address corresponds to the second region of the memory.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A system comprising:
 memory devices to provide data storage corresponding to a range of memory addresses, a first portion of the memory addresses are protected by an error correcting code (ECC) technique and a second portion of the memory addresses are not protected by the ECC technique;   a memory control device coupled with the memory devices, the memory control device having a plurality of processing paths, wherein a first set of the processing paths operate to apply the ECC technique to data and a second set of the processing paths operate to cause the data to be stored without applying the ECC technique, the memory control device to selectively apply the ECC technique based on an address corresponding to a memory access request.   
     
     
         2 . The system of  claim 1  wherein the memory access request comprises a read request. 
     
     
         3 . The system of  claim 1  wherein the memory access request comprises a write request. 
     
     
         4 . The system of  claim 1  wherein the second portion of the memory addresses is configurable. 
     
     
         5 . The system of  claim 1  wherein the second portion of the memory addresses is utilized to store graphics data. 
     
     
         6 . The system of  claim 1  wherein the second portion of the memory addresses reside in an expended memory region. 
     
     
         7 . The system of  claim 1  wherein the memory devices comprise dynamic random access memory (DRAM) devices. 
     
     
         8 . A method comprising:
 receiving a memory access request having an associated address;   determining whether the address corresponds to a first region of a memory for which error correcting code (ECC) techniques are applied or a second region of the memory for which ECC techniques are not applied;   processing the memory access utilizing ECC techniques if the address corresponds to the first region of the memory;   processing the memory access without utilizing the ECC techniques if the address corresponds to the second region of the memory.   
     
     
         9 . The method of  claim 8  wherein the memory access comprises a read operation. 
     
     
         10 . The method of  claim 8  wherein the memory access comprises a write operation. 
     
     
         11 . The method of  claim 8  wherein determining whether the address corresponds to a first region of a memory for which error correcting code (ECC) techniques are applied or a second region of the memory for which ECC techniques are not applied comprises comparing the address to at least two addresses stored in registers that correspond to boundaries of the second region of the memory. 
     
     
         12 . The method of  claim 8  wherein the processing of the memory access request comprises selecting one of a plurality of paths through a memory controller corresponding to whether or not ECC techniques are applied to the memory access. 
     
     
         13 . The method of  claim 8  wherein the second region of the memory addresses is utilized to store graphics data. 
     
     
         14 . The method of  claim 8  wherein the second region of the memory addresses reside in an expended memory region. 
     
     
         15 . An apparatus comprising:
 a first interface to communicate with processing circuitry;   a second interface to communicate with memory devices;   control circuitry coupled with the first interface and the second interface, the control circuitry to receive a memory access request having an associated address via the first interface, to determine whether the address corresponds to a first region of a memory for which error correcting code (ECC) techniques are applied or a second region of the memory for which ECC techniques are not applied, to process the memory access utilizing ECC techniques if the address corresponds to the first region of the memory, and to process the memory access without utilizing the ECC techniques if the address corresponds to the second region of the memory.   
     
     
         16 . The apparatus of  claim 15  wherein determining whether the address corresponds to a first region of a memory for which error correcting code (ECC) techniques are applied or a second region of the memory for which ECC techniques are not applied comprises comparing the address to at least two addresses stored in registers that correspond to boundaries of the second region of the memory. 
     
     
         17 . The apparatus of  claim 15  wherein the processing of the memory access request comprises selecting one of a plurality of paths through a memory controller corresponding to whether or not ECC techniques are applied to the memory access. 
     
     
         18 . The apparatus of  claim 15  wherein the second region of the memory addresses is utilized to store graphics data. 
     
     
         19 . The apparatus of  claim 15  wherein the memory devices comprise dynamic random access memory (DRAM) devices. 
     
     
         20 . The apparatus of  claim 19  wherein the DRAM devices comprise DDR-4 compliant devices.

Join the waitlist — get patent alerts

Track US2014157043A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.