Diagnostic testing for a double-pumped memory array

Abstract

A semiconductor chip and method for diagnostic testing of combinational logic in a logic and array system including Logic Built in Self Test (LBIST) diagnostics are provided. The semiconductor chip includes a logic and array system, an LBIST system, a clocking module, and an addressing module. The method for diagnostic testing includes providing an initialization pattern to an array in the logic and array system, applying a diagnostic control setup, and running the diagnostic test. The diagnostic control setup includes firing a clock every diagnostic test clock cycle and selecting an address from a subset of an address space.

What is claimed is: 
     
         1 . A method for testing an array and logic, comprising:
 providing an initialization pattern to an array in a logic and array system;   applying a diagnostic control setup wherein said setup includes firing a clock every diagnostic test clock cycle and selecting an address from a subset of an address space; and   running a diagnostic test of a combinational logic in the logic and array system;   
     
     
         2 . The method of  claim 1 , wherein using a data path which is a functional path passing through the array in a functional mode. 
     
     
         3 . The method of  claim 1 , wherein the address includes only one address. 
     
     
         4 . The method of  claim 1 , wherein applying the diagnostic control setup includes a read and a write occurring every cycle during the diagnostic test. 
     
     
         5 . The method of  claim 1 , wherein the diagnostic test is LBIST. 
     
     
         6 . The method of  claim 1 , wherein running LBIST testing of the combinational logic in the logic and array system includes analyzing test coverage of the combinational logic. 
     
     
         7 . The method of  claim 6 , further including updating the LBIST control setup responsive to inadequate test coverage of the combinational logic. 
     
     
         8 . The method of  claim 6 , further including providing final test data responsive to adequate test coverage of the combinational logic. 
     
     
         9 . The method of  claim 1 , wherein running LBIST testing of the combinational logic includes AC and DC testing of the combinational logic in the logic and array system.