Memory device and method for manufacturing the same

Abstract

According to one embodiment, a memory device includes a nanomaterial assembly layer, a first electrode layer and a second electrode layer. The nanomaterial assembly layer is formed of an assembly of a plurality of micro conductors via gaps between the micro conductors. The first electrode layer is provided on the nanomaterial assembly layer. The second electrode layer is provided on the first electrode layer.

What is claimed is: 
     
         1 . A method for manufacturing a memory device, comprising:
 forming a nanomaterial assembly layer formed of an assembly of a plurality of micro conductors via gaps between the micro conductors;   forming a first electrode layer on the nanomaterial assembly layer by depositing a conductive material by a first method in which a coverage is relatively low; and   forming a second electrode layer on the first electrode layer by depositing a conductive material by a second method in which the coverage is relatively high.   
     
     
         2 . The method according to  claim 1 , further comprising:
 forming a hard mask layer on the second electrode layer;   forming a resist film on the hard mask layer;   forming a resist pattern by selectively removing the resist film;   patterning the hard mask layer by etching using the resist pattern as a mask; and   forming pillars by selectively removing the second electrode layer, the first electrode layer, and the nanomaterial assembly layer by etching using the patterned hard mask as the mask,
 when a defect occurs in the resist pattern, the resist pattern being removed using a chemical solution, and the forming the resist film and the forming the resist pattern being carried out again. 
   
     
     
         3 . The method according to  claim 1 , wherein the first method is a physical vapor deposition method, and the second method is a chemical vapor deposition method. 
     
     
         4 . The method according to  claim 1 , wherein the micro conductors are carbon nanotubes. 
     
     
         5 . A method for manufacturing a memory device, comprising:
 forming a nanomaterial assembly layer formed of an assembly of a plurality of micro conductors via gaps between the micro conductors;   forming an electrode layer on the nanomaterial assembly layer by depositing a conductive material by a first method in which a coverage is relatively low;   forming a silicon nitride layer on the electrode layer by depositing silicon nitride by a second method in which the coverage is relatively high;   forming a hard mask layer on the silicon nitride layer;   forming a resist film on the hard mask layer;   forming a resist pattern by selectively removing the resist film;   patterning the hard mask layer by etching using the resist pattern as a mask;   forming pillars by selectively removing the silicon nitride layer, the electrode layer, and the nanomaterial assembly layer by etching using the patterned hard mask as the mask;   forming an inter-layer insulating film around the pillars;   flattening a top surface of the inter-layer insulating film by performing a flattening process using the electrode layer as a stopper; and   removing the hard mask and the silicon nitride film,
 when a defect occurs in the resist pattern, the resist pattern being removed using a chemical solution, and the forming the resist film and the forming the resist pattern being carried out again. 
   
     
     
         6 . The method according to  claim 5 , wherein the first method is a physical vapor deposition method, and the second method is a chemical vapor deposition method. 
     
     
         7 . The method according to  claim 5 , wherein the micro conductors are carbon nanotubes.