Memory Device Interconnects and Method of Manufacture

Abstract

An integrated circuit memory device, in one embodiment, includes a substrate having a plurality of bit lines. A first and second inter-level dielectric layer are successively disposed on the substrate. Each of a plurality of source lines extend through the first inter-level dielectric layer. Each of a plurality of source line vias extend through the second inter-level dielectric layer to each respective one of the plurality of source lines. Each of the plurality of staggered bit line contacts extend through the first and second inter-level dielectric layes to respective bit lines.

What is claimed is: 
     
         1 . An integrated circuit memory device comprising:
 a substrate having a plurality of bit lines;   a first inter-level dielectric layer disposed on the substrate;   a second inter-level dielectric layer disposed on the first inter-level dielectric layer;   a plurality of source lines that extend through the first inter-level dielectric layer;   a plurality of source line vias that extend through the second inter-level dielectric layer to each respective one of the plurality of source lines;   a plurality of bit line contacts that extend through the first inter-level dielectric layer and second inter-level dielectric layer to each respective one of the plurality of bit lines; and   a metallization layer coupled to one or more of the plurality of source line vias and one or more of the plurality of bit line contacts.   
     
     
         2 . The integrated circuit memory device of  claim 1 , wherein the plurality of source lines are formed from a first metal layer. 
     
     
         3 . The integrated circuit memory device of  claim 2 , wherein the plurality of bit line contacts and the plurality of source line vias are formed from a second metal layer. 
     
     
         4 . The integrated circuit memory device of  claim 1 , wherein the plurality of bit line contacts and plurality of bit line vias are staggered so that adjacent ones of the bit line contacts and bit line vias are not in a same row. 
     
     
         5 . The integrated circuit memory device of  claim 1 , wherein the plurality of bit line contacts, the plurality of source lines and the plurality of source line vias are formed from a metal or metal alloy. 
     
     
         6 . The integrated circuit memory device of  claim 1 , wherein the plurality of bit line contacts, the plurality of source lines and the plurality of source line vias are comprised of one or more metals selected from the group consisting of tungsten, titanium, and titanium nitride. 
     
     
         7 . The integrated circuit memory device of  claim 1 , wherein each of the plurality of bit line contacts are tapered. 
     
     
         8 . The integrated circuit memory device of  claim 1 , wherein each of the plurality of source lines and each of the plurality of source line vias are tapered. 
     
     
         9 . A method of fabricating an integrated circuit memory device comprising:
 depositing a first inter-level dielectric layer on a substrate having a plurality of bit lines;   etching a plurality of source line trenches in the first inter-level dielectric layer;   forming a plurality of source lines in the plurality of source line trenches from a first metal layer;   depositing a second inter-level dielectric layer on the first inter-level dielectric layer;   etching a plurality of source line via openings in the second inter-level dielectric layer that each extend to a respective one of the plurality of source lines and a plurality of staggered bit line via openings in the second inter-level dielectric layer that each extend to a respective one of the plurality of staggered bit line contacts;   etching a plurality of staggered bit line contact openings in the second inter-level dielectric layer and the first inter-level dielectric layer that each extend to a respective one of the plurality of bit lines; and   forming a plurality of source line vias in the plurality of source line via openings and a plurality of staggered bit line contacts in the plurality of staggered bit line contact openings from a second metal layer.   
     
     
         10 . The method according to  claim 9 , wherein forming the plurality of source lines comprises:
 depositing the first metal layer after etching the source line trenches; and   removing a portion of the first metal layer until the first metal layer only remains in the source line trenches.   
     
     
         11 . The method according to  claim 9 , wherein forming the plurality of source line vias and the plurality of staggered bit line contacts comprises:
 depositing the second metal layer after etching the source line via openings and the staggered bit line contact openings; and   removing a portion of the second metal layer until the second metal layer only remains in the source line via openings and staggered bit line contact openings.   
     
     
         12 . The method according to  claim 9 , wherein:
 the source line trenches are etched using a first mask;   the source line via openings are etched using a second mask; and   the staggered bit line contact openings are etched using a third mask.   
     
     
         13 . The method according to  claims 9 , wherein each of the plurality of stagered bit line contacts are tapered. 
     
     
         15 . The method according to  claim 9 , wherein the first metal layer is tungsten, titanium, titanium nitrate or a multilayer of titanium, titanium nitride and tungsten. 
     
     
         16 . The method according to  claim 9 , wherein the second metal layer is tungsten, titanium, titanium nitrate or a multilayer of titanium, titanium nitride and tungsten.