Inter-Layer Insulator for Electronic Devices and Apparatus for Forming Same

Abstract

A semiconducting device utilizing air-gaps for inter-layer insulation and methods of producing the device are described. The device may be produced by forming a sacrificial layer between two structures. A porous membrane layer is then formed over the sacrificial layer. The membrane layer is porous to an etch product, which allows for the subsequent etching of the sacrificial layer leaving an air gap between the device structures and the membrane intact. The device may also include a cap layer formed above the device structures and the membrane.

What is claimed is: 
     
         1 . A method of forming an air-gap in a semiconducting device, comprising:
 forming a sacrificial layer between a first structure and a second structure;   forming a membrane layer over the sacrificial layer, the membrane being porous to an etch product; and   etching the sacrificial layer through the membrane and between the first structure and the second structure to create an air gap, wherein the sacrificial layer is etched without etching the membrane layer.   
     
     
         2 . The method of  claim 1 , further comprising forming a buffer layer between the sacrificial layer and the first and second structures. 
     
     
         3 . The method of  claim 1 , further comprising forming a cap layer above the membrane layer. 
     
     
         4 . The method of  claim 3 , wherein the cap layer comprises a dielectric material. 
     
     
         5 . The method of  claim 1 , further comprising planerizing the sacrificial layer prior to forming the membrane material. 
     
     
         6 . The method of  claim 1 , wherein the membrane layer is formed such that it overlaps a portion of the first structure and a portion of the second structure. 
     
     
         7 . The method of  claim 1 , wherein the air gap functions as an insulator between the first and second structures. 
     
     
         8 . The method of  claim 1 , wherein at least one of the first and second structures comprises a transistor, a capacitor, an electrode, a contact, or an interconnect. 
     
     
         9 . The method of  claim 1 , wherein the membrane layer is formed by sputtering or deposition. 
     
     
         10 . The method of  claim 1 , wherein the sacrificial layer comprises Silicon, Aluminum, Germanium, Tungsten, photo resist, or an organic film. 
     
     
         11 . A semiconducting device, comprising:
 a first structure and a second structure;   an air gap disposed between the first structure and the second structure; and   a membrane layer disposed above the air gap and between the first and second structures, wherein the membrane layer is porous to an etching product, the etching product being capable of etching a sacrificial layer without etching the membrane layer.   
     
     
         12 . The device of  claim 11 , further comprising a buffer layer disposed between the membrane layer and the first and second structures. 
     
     
         13 . The device of  claim 11 , further comprising a cap layer disposed above the membrane layer. 
     
     
         14 . The device of  claim 13 , wherein the cap layer comprises a dielectric material. 
     
     
         15 . The device of  claim 11 , wherein the membrane layer comprises a native oxide. 
     
     
         16 . The device of  claim 11 , wherein the membrane layer overlaps a portion of the first structure and a portion of the second structure. 
     
     
         17 . The device of  claim 11 , wherein the air gap functions as an insulator between the first and second structures. 
     
     
         18 . The device of  claim 11 , wherein one of the first and second structures comprises a transistor, a capacitor, an electrode, a contact, or an interconnect. 
     
     
         19 . The device of  claim 11 , wherein the membrane layer is formed by sputtering or deposition. 
     
     
         20 . The device of  claim 11 , wherein membrane layer is configured to be permeable to an etching product that etches Silicon, Aluminum, Germanium, Tungsten, photo resist, or an organic film. 
     
     
         21 . An apparatus, comprising:
 a semiconductor fabrication module; and   a semiconductor fabrication controller configured to cause the semiconducting fabrication module to:
 form a sacrificial layer between a first structure and a second structure of a semiconductor device; 
 form a membrane layer over the sacrificial layer, the membrane being porous to an etch product; and 
 etch the sacrificial layer through the membrane and between the first structure and the second structure to create an air gap, wherein the sacrificial layer is etched without etching the membrane layer. 
   
     
     
         22 . A semiconducting device, comprising:
 a first structure and a second structure;   an air gap disposed between the first structure and the second structure;   a membrane layer disposed above the air gap and between the first and second structures, wherein the membrane layer is porous to an etching product, the etching product being capable of etching a sacrificial layer without etching the membrane layer; and   a buffer layer disposed on the first and second structures, wherein the buffer layer is configured to not react with the etching product and to act as a protective layer with respect to the first and second structures.