Integrated circuit device having a resistor and method of manufacturing the same

Abstract

In an integrated circuit device and method of manufacturing the same, a resistor pattern is positioned on a device isolation layer of a substrate. The resistor pattern includes a resistor body positioned in a recess portion of the device isolation layer and a connector making contact with the resistor body and positioned on the device isolation layer around the recess portion. The connector has a metal silicide pattern having electric resistance lower than that of the resistor body at an upper portion. A gate pattern is positioned on the active region of the substrate and includes the metal silicide pattern at an upper portion. A resistor interconnection is provided to make contact with the connector of the resistor pattern. A contact resistance between the connector and the resistor interconnection is reduced.

What is claimed is: 
     
         1 . An integrated circuit device comprising:
 a substrate having an active region defined by a device isolation layer;   a resistor pattern formed on the device isolation layer, the resistor pattern including a resistor body positioned in a recess portion of the device isolation layer and at least a connector making contact with the resistor body and positioned on the device isolation layer around the recess portion, the connector having a metal silicide pattern having electric resistance lower than that of the resistor body at an upper portion thereof;   a gate pattern formed on the active region of the substrate, the gate pattern including the metal silicide pattern at an upper portion thereof; and   a resistor interconnection making contact with the connector of the resistor pattern.   
     
     
         2 . The integrated circuit device of  claim 1 , wherein the connector includes a stack structure in which a dielectric pattern, a first conductive pattern, a second conductive pattern and the metal silicide pattern are sequentially stacked and the resistor body includes the second conductive pattern. 
     
     
         3 . The integrated circuit device of  claim 2 , wherein the first conductive pattern includes carbon (C)-doped polysilicon and the second conductive pattern includes phosphor (P)-doped polysilicon. 
     
     
         4 . The integrated circuit device of  claim 2 , wherein the second conductive pattern is continuously arranged across the resistor body and the connector and the connector and the resistor body has a stepped portion of about 800 Å to about 1,000 Å. 
     
     
         5 . The integrated circuit device of  claim 2 , wherein the gate pattern includes a tunnel insulation layer, a floating gate pattern, the dielectric pattern, the first and the second conductive patterns that are sequentially stacked on the cell area of the substrate. 
     
     
         6 . An integrated circuit device, comprising:
 one or more device isolation layers formed on a cell area and a peripheral area of a substrate;   a resistor pattern having a resistor body having a first electric resistance and a connector having a second electric resistance lower than the first electric resistance, formed on the device isolation layers of a resistor portion of the peripheral area of the substrate; and   a resistor interconnection formed to contact the connector of the resistor pattern to reduce a contact resistance therebetween.   
     
     
         7 . The integrated circuit device of  claim 6 , wherein one or more gate patterns are formed on active regions of the cell area of the substrate, and the device isolation layers are formed in field regions of the cell area between the adjacent active regions. 
     
     
         8 . The integrated circuit device of  claim 7 , wherein a floating gate pattern of the gate pattern is formed to be disposed between the device isolation layers such that an upper portion of the floating gate pattern of the gate pattern is exposed from an upper portion of one or more the device isolation layers. 
     
     
         9 . The integrated circuit device of  claim 6 , wherein a recess portion and a protrusion portion are formed in the respective device isolation layers such that the resistor body is on the recess portion and the protrusion portion and the connector ids formed on the protrusion portion to have a depth of recess with the resistor body in the recess portion.