Nonvolatile memory device

Abstract

According to one embodiment, nonvolatile memory device includes a semiconductor layer, a conductive layer and a resistance change layer. The semiconductor layer has an impurity concentration less than 1×10 19 cm −3 . The resistance change layer is provided between the semiconductor layer and the conductive layer. The resistance change layer includes a fixed charge. The resistance change layer is reversibly transitionable between a first state and a second state by at least one selected from a current supplied via the semiconductor layer and the conductive layer and a voltage applied via the semiconductor layer and the conductive layer. A resistance of the resistance change layer in the second state is higher than a resistance of the resistance change layer in the first state.

What is claimed is: 
     
         1 . A nonvolatile memory device, comprising:
 a semiconductor layer having an impurity concentration less than 1×10 19  cm −3 ;   a conductive layer; and   a resistance change layer provided between the semiconductor layer and the conductive layer, the resistance change layer including a fixed charge, the resistance change layer being reversibly transitionable between a first state and a second state by at least one selected from a current supplied via the semiconductor layer and the conductive layer and a voltage applied via the semiconductor layer and the conductive layer, a resistance of the resistance change layer in the second state being higher than a resistance of the resistance change layer in the first state.   
     
     
         2 . The device according to  claim 1 , wherein
 the semiconductor layer is a p type, and   the fixed charge includes nitrogen.   
     
     
         3 . The device according to  claim 1 , wherein
 the semiconductor layer is an n type, and   the fixed charge includes at least one selected from the group consisting of aluminum, La (lanthanum), Ce (cerium), Pr (praseodymium), Nd (neodymium), Pm (promethium), Sm (samarium), Eu (europium), Gd (gadolinium), Tb (terbium), Dy (dysprosium), Ho (holmium), Er (erbium), Tm (thulium), Yb (ytterbium), and Lu (lutetium).   
     
     
         4 . The device according to  claim 1 , wherein the semiconductor layer includes poly silicon. 
     
     
         5 . The device according to  claim 1 , wherein an electrostatic capacitance between the semiconductor layer and the conductive layer is configured to change in accordance with a voltage between the semiconductor layer and the conductive layer. 
     
     
         6 . The device according to  claim 1 , wherein a depletion layer is configured to be generated in the semiconductor layer. 
     
     
         7 . The device according to  claim 1 , wherein the impurity concentration in the semiconductor layer is not more than 1×10 18  cm −3 . 
     
     
         8 . The device according to  claim 1 , wherein the impurity concentration in the semiconductor layer is not more than 1×10 17  cm −3 . 
     
     
         9 . The device according to  claim 1 , wherein the resistance change layer includes an oxide including at least one selected from the group consisting of Hf, Ni, Ta, Ti, W, Cu, Nb, Mn, Fe, Zr, Al and Co. 
     
     
         10 . The device according to  claim 1 , further comprising:
 a first interconnect; and   a second interconnect,   the semiconductor layer, the conductive layer and the resistance change layer being provided between the first interconnect and the second interconnect.   
     
     
         11 . A nonvolatile memory device, comprising:
 a semiconductor layer having an impurity concentration less than 1×10 19  cm −3 ;   a conductive layer;   a resistance change layer provided between the semiconductor layer and the conductive layer, the resistance change layer being reversibly transitionable between a first state and a second state by at least one selected from a current supplied via the semiconductor layer and the conductive layer and a voltage applied via the semiconductor layer and the conductive layer, a resistance of the resistance change layer in the second state being higher than a resistance of the resistance change layer in the first state; and   an interface portion provided between the semiconductor layer and the resistance change layer, the interface portion including a dipole.   
     
     
         12 . The device according to  claim 11 , wherein
 the semiconductor layer is an n type, and   the interface portion includes at least one selected from hafnium oxide, aluminum oxide, magnesium oxide launthanum oxide, cerium oxide, praseodymium oxide, neodymium oxide, promethium oxide, samarium oxide, europium oxide, gadolinium oxide, terbium oxide, dysprosium oxide, holmium oxide, erbium oxide, thulium oxide, ytterbium oxide, and lutetium oxide.   
     
     
         13 . The device according to  claim 11 , wherein the semiconductor layer includes a poly silicon. 
     
     
         14 . The device according to  claim 11 , wherein an electrostatic capacitance between the semiconductor layer and the conductive layer is configured to change in accordance with a voltage between the semiconductor layer and the conductive layer. 
     
     
         15 . The device according to  claim 11 , wherein a depletion layer is configured to be generated in the semiconductor layer. 
     
     
         16 . The device according to  claim 11 , wherein the impurity concentration in the semiconductor layer is not more than 1×10 18  cm −3 . 
     
     
         17 . The device according to  claim 11 , wherein the resistance change layer may includes an oxide including at least one selected from the group consisting of Hf, Ni, Ta, Ti, W, Cu, Nb, Mn, Fe, Zr, Al and Co. 
     
     
         18 . The device according to  claim 11 , further comprising:
 a first interconnect; and   a second interconnect,   the semiconductor layer, the conductive layer and the resistance change layer being provided between the first interconnect and the second interconnect.