Vertical System Integration

Abstract

The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use and not necessarily limited in its use to a specific application. The VSI method of integration lowers the cost difference between lower volume custom electronic products and high volume generic use electronic products by eliminating or reducing circuit design, layout, tooling and fabrication costs.

What is claimed is: 
     
         1 . A method of using a stacked integrated circuit comprising a plurality of bare die integrated circuits in a stacked relationship, the method comprising:
 placing the stacked integrated circuit in proximity to at least one other stacked integrated circuit, thereby causing wireless communication between the stacked integrated circuits to occur.   
     
     
         2 . The method of  claim 1 , wherein one of the stacked integrated circuits comprises a wireless interconnection processor, comprising the wireless interconnection processor interrogating at least one other stacked integrated circuit in proximity thereto. 
     
     
         3 . The method of  claim 2 , wherein said at least one other stacked integrated circuit comprises a visual indicator, comprising activating the visual indicator in response to said interrogating. 
     
     
         4 . The method of  claim 3 , comprising a user recognizing activation of the visual indicator and in response thereto placing the at least one stacked integrated circuit in operating relation to an electronic device. 
     
     
         5 . The method of  claim 1 , wherein at least one of the stacked integrated circuits comprises IC devices, said IC devices comprising at least one of the following:
 transistors, memory cells, resistors, capacitors, inductors, radio frequency antennas and horizontal interconnections.   
     
     
         6 . The method of  claim 5 , wherein the IC devices comprise at least two of the following:
 transistors, memory cells, resistors, capacitors, inductors, radio frequency antennas and horizontal interconnections.   
     
     
         7 . The method of  claim 5 , wherein the IC devices comprise all of the following:
 transistors, memory cells, resistors, capacitors, inductors, radio frequency antennas and horizontal interconnections.   
     
     
         8 . The method of  claim 1 , wherein, for at least one of the stacked integrated circuits, the stacked integrated circuit is made without fabrication of a circuit layer specific to the function of the particular stacked integrated circuit. 
     
     
         9 . The method of  claim 1 , wherein, for at least one of the stacked integrated circuits, fewer than all of the circuit layers are fabricated for the specific function of the particular stacked integrated circuit. 
     
     
         10 . The method of  claim 1 , wherein at least one of the stacked integrated circuits comprises a plurality of circuit layers, IC device fabrication having been performed on the backside of one or more of said circuit layers. 
     
     
         11 . The method of  claim 1 , wherein at least one of the stacked integrated circuits comprises a plurality of circuit layers, the circuit layers having been bonded using bonding layers made from two or more metal films one of which has a lower melting temperature and which will diffuse with an immediately adjacent film. 
     
     
         12 . The method of  claim 1 , wherein, for at least one of the stacked integrated circuits, an application-specific function of the stacked integrated circuit derives from the choice and quantity of circuit layers chosen from previously-fabricated, non-application-specific circuit layers. 
     
     
         13 . The method of  claim 1 , wherein at least one of the stacked integrated circuits comprises an IC substrate and interconnections formed between circuitry on a frontside of the IC substrate with the circuitry formed on a backside of the IC substrate. 
     
     
         14 . The method of  claim 1 , wherein at least one of the stacked integrated circuits comprises a stacked programmable logic device having at least one of a programmable gate circuit layer and a memory circuit layer. 
     
     
         15 . A method of using a stacked integrated circuit comprising:
 placing the stacked integrated circuit in proximity to at least one other stacked integrated circuit, thereby causing to occur wireless communication of digital data from one of the stacked integrated circuit and the at least one other stacked integrated circuit to another of the stacked integrated circuit and the at least one other stacked integrated circuit.   
     
     
         16 . A method of using a stacked integrated circuit comprising:
 detecting placement of the stacked integrated circuit in proximity to at least one other stacked integrated circuit, thereby causing wireless communication between the stacked integrated circuits to occur; and   thereafter detecting removal of the stacked integrated circuit from proximity of the at least one other stacked integrated circuit.   
     
     
         17 . A method of using a stacked integrated circuit comprising a plurality of tightly-coupled bare die integrated circuits in a stacked relationship, the method comprising:
 placing the stacked integrated circuit in proximity to at least one other stacked integrated circuit, thereby causing wireless communication between the stacked integrated circuits to occur.