Method for manufacturing thin film transistor, and thin film transistor thereof

Abstract

The present invention relates to the field of liquid crystal display, and provides a method for manufacturing a TFT and the TFT thereof. The TFT comprises: a substrate; a gate electrode with a three-dimensional structure formed on the substrate; a gate insulating layer for covering the gate electrode; a semiconductor layer formed on the gate insulating layer; a buffer layer formed on the semiconductor layer; and source and drain electrodes formed on the buffer layer, wherein the semiconductor layer of the TFT is of a three-dimensional structure. According to the present invention, it is able to reduce the driving voltage, the power consumption of the driving circuit and the area occupied by the TFT, and to increase the light transmission rate.

What is claimed is: 
     
         1 . A method for manufacturing a TFT (Thin Film Transistor), comprising the steps of:
 providing a substrate;   forming a gate electrode with a three-dimensional structure on the substrate;   forming a gate insulating layer for covering the gate electrode on the substrate on which the gate electrode is formed;   forming a semiconductor layer on the substrate on which the gate insulating layer is formed;   forming a buffer layer on the substrate on which the semiconductor layer is formed; and   forming a metal layer on the substrate on which the buffer layer is formed, and treating the metal layer by a patterning process to form source and drain electrodes,   wherein the semiconductor layer of the TFT is of a three-dimensional structure.   
     
     
         2 . The method according to  claim 1 , wherein the three-dimensional structure of the gate electrode is a cuboid or cube. 
     
     
         3 . The method according to  claim 1 , wherein the three-dimensional structure of the semiconductor layer is an inverted-U slot structure covering the gate electrode. 
     
     
         4 . The method according to  claim 3 , wherein a portion of the semiconductor layer between the source and drain electrodes forms a channel, a length of the channel is the distance between the source and drain electrodes, and a width of the channel≧(a width of the gate electrode+2*a height of the gate electrode). 
     
     
         5 . The method according to  claim 2 , wherein the step of forming a gate electrode with a three-dimensional structure on the substrate comprises:
 depositing a first metal layer on the substrate; and   treating the first metal layer by a patterning process to form the gate electrode with a three-dimensional structure.   
     
     
         6 . The method according to  claim 5 , wherein the first metal layer can be made of ITO, or a metal selected from the group consisting of Cr, Mo, Al, Nd, Mo, W, Ti, Ta and Cu, or an alloy thereof. 
     
     
         7 . The method according to  claim 2 , wherein the step of forming a gate insulating layer for covering the gate electrode on the substrate on which the gate electrode is formed comprises:
 depositing an insulating material layer on the substrate on which the gate electrode with a cuboid structure is formed; and   treating the insulating material layer by a patterning process to form the gate insulating layer on a top face and two side faces of the gate electrode.   
     
     
         8 . The method according to  claim 2 , wherein the step of forming a semiconductor layer on the substrate on which the gate insulating layer comprises:
 depositing a semiconductor material layer on the substrate on which the gate insulating layer is formed; and   treating the semiconductor material layer by a patterning process to form the semiconductor layer on the gate insulating layer.   
     
     
         9 . The method according to  claim 2 , wherein the step of forming a buffer layer on the substrate on which the semiconductor layer is formed comprises:
 depositing an N+ amorphous silicon material layer on the substrate on which the semiconductor layer is formed; and   treating the N+ amorphous silicon material layer by a patterning process to form the buffer layer on the semiconductor layer.   
     
     
         10 . The method according to  claim 2 , wherein the step of forming a metal layer on the substrate on which the buffer layer is formed and treating the metal layer by a patterning process to form source and drain electrodes comprises:
 depositing a second metal layer on the substrate on which the buffer layer is formed; and   treating the second metal layer by a patterning process to form the source and drain electrodes on the buffer layer.   
     
     
         11 . The method according to  claim 10 , wherein the second metal layer can be made of a metal selected from the group consisting of Cr, Mo, Al, Nd, Mo, W, Ti, Ta and Cu, or an alloy thereof. 
     
     
         12 . A TFT (Thin Film Transistor), comprising:
 a substrate;   a gate electrode with a three-dimensional structure formed on the substrate;   a gate insulating layer for covering the gate electrode;   a semiconductor layer formed on the gate insulating layer;   a buffer layer formed on the semiconductor layer; and   source and drain electrodes formed on the buffer layer,   wherein the semiconductor layer of the TFT is of a three-dimensional structure.   
     
     
         13 . The TFT according to  claim 12 , wherein the three-dimensional structure of the gate electrode is a cuboid or cube. 
     
     
         14 . The TFT according to  claim 12 , wherein the three-dimensional structure of the semiconductor layer is an inverted-U slot structure covering the gate electrode. 
     
     
         15 . The TFT according to  claim 13 , wherein a portion of the semiconductor layer between the source and drain electrodes forms a channel, a length of the channel is the distance between the source and drain electrodes, and a width of the channel≧(a width of the gate electrode+2*a height of the gate electrode). 
     
     
         16 . The TFT according to  claim 15 , wherein the channel of the TFT at least comprises three electronic gates.