Adjustable Byte Lane Offset For Memory Module to Reduce Skew

Abstract

Disclosed herein are solutions for addressing the problem of skew of data within a byte lane by factors caused external to the integrated circuit or module providing the data. To compensate for such skew, an on-chip delay is added to the data out paths of those bits in the byte lane with otherwise would arrive early to their destinations. Such on-chip delay is provided delay circuits preferably positioned directly before the output buffers/bond pads of the integrated circuit or module. By intentionally delaying some of the outputs from the integrated circuit or module, external skew is compensated for so that all data in the byte lane arrives at the destination at substantially the same time. In a preferred embodiment, the delay circuits are programmable to allow the integrated circuit or module to be freely tailored to environments having different skew considerations, such as different styles of connectors.

What is claimed is: 
     
         1 . A memory module, comprising:
 a plurality of data paths internal to the memory module and configured to provide data signals in parallel; and   one or more connectors to receive the data signals from the plurality of data paths, the one or more connectors being couplable to a receiving circuit via a plurality of traces external to the memory module, at least one of the one or more connectors having a delay circuit to selectively impose one or more different delays on data signals in its respective data path at a respective output of the one or more connectors to provide a compensating skew to the respective data signal.