Flash memory device and programming method thereof

Abstract

A flash memory device including a memory array, a row decoder and M page buffers is provided, wherein M is an integer greater than 2. The memory array includes a plurality of memory cells and is connected to a plurality of word lines and a plurality of bit lines. The row decoder drives a specific word line among the word lines during an enabling period. Each of the page buffers is connected to N bit lines of the bit lines, and N is an integer equal to or greater than 3. A j th page buffer drives an (N*(j−1)+1) th bit line to an (N*j) th bit line during the enabling period, and one of an (i−1) th bit line and an (i+1) th bit line is not driven when an i th bit line is not driven, wherein j is an integer and 1≦j≦M, and i is an integer and 1<i<M*N.

What is claimed is: 
     
         1 . A flash memory device, comprising:
 a memory cell array, comprising a plurality of memory cells, and electrically connected to a plurality of word lines and a plurality of bit lines;   a row decoder, for driving a specific word line among the word lines during an enabling period; and   M page buffers, each of the page buffers being electrically connected to N bit lines of the bit lines, wherein a j th  page buffer drives an (N*(j−1)+1) th  bit line to an (N*j) th  bit line during the enabling period, so as to program the memory cells electrically connected to the specific word line one-by-one, and one of an (i−1) th  bit line and an (i+1) th  bit line is not driven when an i th  bit line is not driven, wherein M is an integer greater than 2, N is an integer equal to or greater than 3, j is an integer and 1≦j≦M, and i is an integer and 1<i<M*N.   
     
     
         2 . The flash memory device as claimed in  claim 1 , wherein the memory cell array is further electrically connected to a string selection line and a ground selection line, and the row decoder respectively provides a power voltage and a ground voltage to the string selection line and the ground selection line during the enabling period, provides a program voltage to the specific word line, and provides a pass voltage to the other word lines. 
     
     
         3 . The flash memory device as claimed in  claim 1 , wherein the j th  page buffer sequentially provides a ground voltage to the (N*(j−1)+1) th  bit line to the (N*j) th  bit line during the enabling period, and the bit lines without receiving the ground voltage in the (N*(j−1)+1) th  bit line to the (N*j) th  bit line are biased at a power voltage. 
     
     
         4 . The flash memory device as claimed in  claim 1 , wherein the memory cell array is an NAND memory cell array. 
     
     
         5 . A programming method of a flash memory device, wherein the flash memory device comprises a memory cell array electrically connected to a plurality of word lines and a plurality of bit lines, and the memory cell array comprises a plurality of memory cells, and the programming method of the flash memory device comprising:
 driving a specific word line among the word lines during an enabling period;   electrically connecting M page buffers through the bit lines, and each of the page buffers being electrically connected to N bit lines of the bit lines, wherein M is an integer greater than 2, and N is an integer equal to or greater than 3; and   driving an (N*(j−1)+1) th  bit line to an (N*j) th  bit line by a j th  page buffer during the enabling period, so as to program the memory cells electrically connected to the specific word line one-by-one, wherein one of an (i−1) th  bit line and an (i+1) th  bit line is not driven when an i th  bit line is not driven, j is an integer and 1≦j≦M, and i is an integer and 1<i<M*N.   
     
     
         6 . The programming method of the flash memory device as claimed in  claim 5 , wherein the memory cell array is further electrically connected to a string selection line and a ground selection line, and the step of driving the specific word line among the word lines during the enabling period comprises:
 providing a power voltage to the string selection line;   providing a ground voltage to the ground selection line;   providing a program voltage to the specific word line; and   providing a pass voltage to the other word lines.   
     
     
         7 . The programming method of the flash memory device as claimed in  claim 5 , wherein the step of driving the (N*(j−1)+1) th  bit line to the (N *j) th  bit line by the j th  page buffer during the enabling period comprises:
 sequentially providing a ground voltage to the (N*(j−1)+1) th  bit line to the (N*j) th  bit line by the j th  page buffer during the enabling period; and 
 biasing the bit lines without receiving the ground voltage in the (N*(j−1)+1) th  bit line to the (N*j) th  bit line at a power voltage during the enabling period. 
 
     
     
         8 . The programming method of the flash memory device as claimed in  claim 5 , wherein the memory cell array is an NAND memory cell array.