Techniques and configurations for recessed semiconductor substrates

Abstract

Embodiments of the present disclosure provide a method comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, electrically coupling one or more dies to the redistribution layer, forming a molding compound on the semiconductor substrate, recessing the second surface of the semiconductor substrate, forming one or more channels through the recessed second surface of the semiconductor substrate to expose the redistribution layer; and forming one or more package interconnect structures in the one or more channels, the one or more package interconnect structures being electrically coupled to the redistribution layer, the one or more package interconnect structures to route electrical signals of the one or more dies. Other embodiments may be described and/or claimed.

1 . An apparatus comprising:
 a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface;   a dielectric film formed between the first surface of the semiconductor substrate and a redistribution layer;   the redistribution layer formed on the dielectric film, only one side of the redistribution layer contacting with the dielectric film;   one or more dies electrically coupled to the redistribution layer;   a molding compound formed on the semiconductor substrate;   one or more channels formed through the second surface of the semiconductor substrate, the one or more channels having a width at the second surface that is at least as large as a largest width of a package interconnect structure; and   one or more of the package interconnect structures disposed in the one or more channels, the one or more package interconnect structures being electrically coupled to the redistribution layer through the one or more channels to route electrical signals of the one or more dies.   
     
     
         2 . The apparatus of  claim 1 , wherein the one or more dies are coupled to the redistribution layer in a flip-chip configuration using one or more bumps. 
     
     
         3 . The apparatus of  claim 1 , wherein the molding compound substantially encapsulates the one or more dies. 
     
     
         4 . The apparatus of  claim 1 , wherein the second surface of the semiconductor substrate is recessed such that the semiconductor substrate has a thickness between about 50 microns and about 300 microns. 
     
     
         5 . The apparatus of  claim 1 , further comprising:
 an underfill layer formed between (i) the one or more dies and (ii) the semiconductor substrate.   
     
     
         6 . The apparatus of  claim 1 , wherein:
 the one or more package interconnect structures comprise solder balls to route electrical signals of the one or more dies; and   the redistribution layer comprises an electrically conductive material to route the electrical signals of the one or more dies.   
     
     
         7 . The apparatus of  claim 1 , wherein:
 the semiconductor substrate comprises silicon;   the one or more dies comprise silicon; and   the one or more channels comprise one or more through-silicon vias.   
     
     
         8 . The apparatus of  claim 7 , wherein:
 the molding compound and the semiconductor substrate have a coefficient of thermal expansion (CTE) that is the same or substantially similar; and   the one or more through-silicon vias are tapered.