Solid state memory (ssm), computer system including an ssm, and method of operating an ssm

Abstract

In one aspect, data is stored in a solid state memory which includes first and second memory layers. A first assessment is executed to determine whether received data is hot data or cold data. Received data which is assessed as hot data during the first assessment is stored in the first memory layer, and received data which is first assessed as cold data during the first assessment is stored in the second memory layer. Further, a second assessment is executed to determine whether the data stored in the first memory layer is hot data or cold data. Data which is then assessed as cold data during the second assessment is migrated from the first memory layer to the second memory layer.

What is claimed is: 
     
         1 . A nonvolatile memory system comprising:
 a first group of memory cells, each of the first group of memory cells having a first number of bits per cell;   a second group of memory cells, each of the second group of memory cells having a second number of bits per cell; and   a controller configured to perform a write operation on the first group of memory cells or on the second group of memory cells based on an access frequency to a logical address in the nonvolatile memory system, the controller being configured to determine whether the number of available memory cells in the first group of memory cells is less than a predetermined number,   wherein, based on a result of the determination, the controller is configured to maintain at least the predetermined number of the available memory cells in the first group of memory cells by moving data from the first group of memory cells to the second group of memory cells.   
     
     
         2 . The nonvolatile memory system of  claim 1 , wherein the controller is configured to write the data to the first group of memory cells or to the second group of memory cells in response to input information from a host connected to the controller of the memory system. 
     
     
         3 . The nonvolatile memory system of  claim 2 , wherein the input information is a write command provided from the host. 
     
     
         4 . The nonvolatile memory system of  claim 1 , wherein the controller is configured to move the data corresponding to the logical address having the access frequency that is lower than a predetermined access frequency from the first group of memory cells to the second group of memory cells, only if the second group of memory cells have available memory cells to receive the data from the first group of memory cells. 
     
     
         5 . A method of storing data to a memory system that includes a first group of memory cells and a second group of memory cells, each of the first group of memory cells having a first number of bits per cell, each of the second group of memory cells having a second number of bits per cell, the method comprising:
 determining an access frequency to a logical address of the memory system;   storing the data corresponding to the logical address in either the first group of memory cells or the second group of memory cells, based on the access frequency; and   maintaining at least a predetermined number of available memory cells in the first group of memory cells by moving the data from the first group of memory cells to the second group of memory cells.   
     
     
         6 . The method of  claim 5 , further comprising determining whether the second group of memory cells has available memory cells to receive the data from the first group of memory cells. 
     
     
         7 . The method of  claim 6 , wherein the moving the data from the first group of memory cells to the second group of memory cells is performed only if the second group of memory cells have the available memory cells. 
     
     
         8 . The method of  claim 5 , wherein the first group of memory cells are single level memory cells and the second group of memory cells are multi-level memory cells. 
     
     
         9 . The method of  claim 5 , wherein the second number is greater than the first number. 
     
     
         10 . The method of  claim 5 , wherein the storing the data comprises translating the logical address into a physical address of one of the first group of memory cells and the second group of memory cells in which the data is to be stored. 
     
     
         11 . The method of  claim 5 , wherein the determining the access frequency comprises determining whether the logical address is accessed during a particular time period. 
     
     
         12 . The method of  claim 5 , wherein the maintaining at least the predetermined number of available memory cells in the first group of memory cells comprises:
 examining the access frequency of the data stored in the first group of memory cell; and   moving the data that has the access frequency that is lower than a predetermined access frequency from the first group of memory cells to the second group of memory cells.   
     
     
         13 . The method of  claim 12 , wherein the examining the access frequency is performed,
 when the number of the available memory cells in the first group of memory cells is less than the predetermined number,   when the memory system is in an idle state in which no read or write request is received from a host device, or an activation ratio or an intensity of the read or write requests is less than a predetermined value; or   periodically, depending on a predetermined time period.   
     
     
         14 . A memory system, comprising:
 a first group of memory cells, each of the first group of memory cells having a first number of bits per cell;   a second group of memory cells, each of the second group of memory cells having a second number of bits per cell; and   the controller configured to maintain at least a predetermined number of available memory cells in the first group of memory cells by moving data from the first group of memory cells to the second group of memory cells.   
     
     
         15 . The memory system of  claim 14 , wherein the data that is moved from the first group of memory cells to the second group of memory cells is selected based on an access frequency to a logical address of the data. 
     
     
         16 . The memory system of  claim 14 , wherein the controller is configured to determine whether the second group of memory cells have available memory cells to receive the data from the first group of memory cells. 
     
     
         17 . The memory system of  claim 16 , wherein the data is moved from the first group of memory cells to the second group of memory cells only if the second group of memory cells have the available memory cells. 
     
     
         18 . The memory system of  claim 14 , wherein the controller is configured to determine whether the number of the available memory cells in the first group of memory cells is less than the predetermined number. 
     
     
         19 . The memory system of  claim 18 , wherein the controller is configured to move the data from the first group of memory cells to the second group of memory cells if the number of the available memory cells in the first group of memory cells is less than the predetermined number. 
     
     
         20 . The memory system of  claim 14 , wherein the first group of memory cells are single-level flash memory cells, and the second group of memory cells are multi-level flash memory cells. 
     
     
         21 . The memory system of  claim 14 , wherein the first group of memory cells use a fine-grain mapping and the second group of memory cells use a coarse-grain mapping such that an operational speed of the first group of memory cells is faster than an operational speed of the second group of memory cells. 
     
     
         22 . The memory system of  claim 14 , wherein the controller moves the data stored in the first group of memory cells to the second group of memory cells if the data stays in the first group of memory cells longer than a predetermined time period. 
     
     
         23 . The memory system of  claim 14 , wherein a first-type data is initially stored in the first group of memory cells and a second-type data is stored in the second group of memory cells, the first-type data having the access frequency that is greater than a predetermined access frequency, the second-type data having the access frequency that is lower than the predetermined access frequency. 
     
     
         24 . The memory system of  claim 23 , wherein the first-type data includes directory information and logging information, and the second-type data includes image files, sound files and program code. 
     
     
         25 . A method of managing data in a memory system that includes a first memory and a second memory, the method comprising:
 determining whether the first memory has a predetermined level of available memory cells; and   maintaining the available memory cells of the first memory above the predetermined level by moving data in the first memory to the second memory.   
     
     
         26 . The method of  claim 25 , wherein the data is moved from the first memory to the second memory only if the second memory has available memory cells to receive the data from the first memory. 
     
     
         27 . The method of  claim 25 , wherein both the first memory and the second memory include multi-level memory cells, the number of bit per cell in the second memory being greater than the number of bit per cell in the first memory. 
     
     
         28 . The method of  claim 25 , wherein the first memory includes single-level memory cells, and the second memory includes multi-level memory cells. 
     
     
         29 . The method of  claim 25 , wherein the first memory and the second memory are a single integrated memory that is divided into a first group and a second group such that the first group is allocated as the first memory and the second group is allocated as the second memory. 
     
     
         30 . The method of  claim 25 , wherein a storage capacity of the second memory is greater than a storage capacity of the first memory.