Self-Aligned Silicide Bottom Plate for EDRAM Applications by Self-Diffusing Metal in CVD/ALD Metal Process

Abstract

In one aspect, a method of fabricating a memory cell capacitor includes the following steps. At least one trench is formed in a silicon wafer. A thin layer of metal is deposited onto the silicon wafer, lining the trench, using a conformal deposition process under conditions sufficient to cause at least a portion of the metal to self-diffuse into portions of the silicon wafer exposed within the trench forming a metal-semiconductor alloy. The metal is removed from the silicon wafer selective to the metal-semiconductor alloy such that the metal-semiconductor alloy remains. The silicon wafer is annealed to react the metal-semiconductor alloy with the silicon wafer to form a silicide, wherein the silicide serves as a bottom electrode of the memory cell capacitor. A dielectric is deposited into the trench covering the bottom electrode. A top electrode is formed in the trench separated from the bottom electrode by the dielectric.

1 . A method of fabricating a memory cell capacitor, comprising the steps of:
 providing a silicon wafer;   forming at least one trench in the silicon wafer;   depositing a thin layer of metal onto the silicon wafer, lining the trench, using a conformal deposition process under conditions sufficient to cause at least a portion of the metal to self-diffuse into portions of the silicon wafer exposed within the trench forming a metal-semiconductor alloy, wherein the metal is deposited to a thickness of from about 5 nanometers to about 20 nanometers;   removing the metal from the silicon wafer selective to the metal-semiconductor alloy such that the metal-semiconductor alloy remains;   annealing the silicon wafer, after the metal has been removed selective to the metal-semiconductor alloy, to react the metal-semiconductor alloy with the silicon wafer to form a silicide, wherein the silicide serves as a bottom electrode of the memory cell capacitor;   depositing a dielectric into the trench covering the bottom electrode; and   forming a top electrode in the trench separated from the bottom electrode by the dielectric, wherein the top electrode comprises titanium and polysilicon.   
     
     
         2 . The method of  claim 1 , wherein the thin metal layer is deposited onto the wafer using chemical vapor deposition or atomic layer deposition. 
     
     
         3 . The method of  claim 1 , wherein the thin metal layer comprises a metal selected from the group consisting of: tungsten, tungsten nitride, tantalum, titanium, and platinum. 
     
     
         4 . The method of  claim 1 , wherein the conditions comprise a deposition temperature of from about 400° C. to about 700° C. 
     
     
         5 . The method of  claim 1 , wherein the metal is removed from the wafer selective to the metal-semiconductor alloy using a wet etching process. 
     
     
         6 . The method of  claim 1 , wherein the silicon wafer is annealed at a temperature of greater than about 700° C. 
     
     
         7 . The method of  claim 1 , wherein the silicon wafer is annealed at a temperature of from about 700° C. to about 1,000° C. 
     
     
         8 . The method of  claim 1 , wherein the dielectric comprises a high-k material. 
     
     
         9 . The method of  claim 8 , wherein the high-k material is selected from the group consisting of: hafnium oxide, hafnium silicate, lanthanum oxide and lanthanum silicate. 
     
     
         10 . (canceled) 
     
     
         11 . (canceled) 
     
     
         12 . The method of  claim 1 , further comprising the steps of:
 forming a pad oxide on the wafer;   forming a pad nitride on the pad oxide;   forming a hardmask on the pad nitride;   patterning the hardmask to form a patterned hardmask; and   using the patterned hardmask to form the trench in the wafer.   
     
     
         13 . The method of  claim 12 , wherein the pad nitride comprises silicon nitride. 
     
     
         14 . The method of  claim 1 , wherein the silicon wafer comprises a silicon-on-insulator (SOI) wafer having an SOI layer separated from a silicon substrate by a buried oxide (BOX), and wherein the trench extends through the SOI layer, through the BOX and partway into the silicon substrate. 
     
     
         15 . The method of  claim 14 , further comprising the step of:
 forming sidewall spacers on vertical surfaces of the trench that cover and protect portions of the SOI layer through which the trench passes.   
     
     
         16 . The method of  claim 15 , wherein the sidewall spacers comprise a nitride material. 
     
     
         17 . The method of  claim 15 , wherein the step of forming the trench in the silicon wafer further comprises the steps of:
 forming the trench to a first depth in the silicon wafer; and   after formation of the sidewall spacers, extending the trench to a second depth in the silicon wafer.   
     
     
         18 . The method of  claim 1 , wherein the trench is formed in the silicon wafer using reactive ion etching. 
     
     
         19 . The method of  claim 1 , further comprising the step of
 etching the trench laterally to increase a width of the trench.   
     
     
         20 . The method of  claim 19 , wherein the trench is etched laterally using a potassium hydroxide wet etch. 
     
     
         21 . The method of  claim 1 , further comprising the step of
 doping the silicon wafer.   
     
     
         22 . The method of  claim 21 , wherein the silicon wafer is doped with boron, arsenic or phosphorous at a concentration of from about 2×10 18  cm 3  to about 5×10 20  cm 3 .