Differential moscap device

Abstract

A differential MOS capacitor structure includes two capacitor sections coupled to different gates and operating using different signals. The respective signals may be 180° out of phase. The capacitor sections of the differential capacitor each include two or more upper capacitor plates disposed over a single common lower capacitor plate which serves as a common node thereby preventing parasitic capacitance. The upper capacitor plates of a first capacitor section are adjacent one another with no electrical components disposed between them. The upper capacitor plates of a second capacitor section are adjacent one another with no electrical components disposed between them. The upper capacitor plates are formed of a plurality of stacked conductive layers in some embodiments.

What is claimed is: 
     
         1 . A differential MOS capacitor semiconductor device comprising:
 a first capacitor section coupled to a first gate and including a plurality of first capacitor upper electrodes coupled to said first gate;   a second capacitor section coupled to a second gate and including a plurality of second capacitor upper electrodes coupled to said first gate; and   a conductive plate that serves as a common bottom capacitor plate for each of said first and second capacitor sections and is formed in or on a substrate surface,   wherein said plurality of first capacitor upper electrodes and said plurality of second capacitor upper electrodes are each disposed over said common bottom capacitor plate.   
     
     
         2 . The differential MOS capacitor semiconductor device as in  claim 1 , wherein no electrical components are interposed between said first capacitor upper electrodes of said plurality of first capacitor upper electrodes; no electrical components are interposed between said second capacitor upper electrodes of said plurality of second capacitor upper electrodes, and no electrical components are interposed between said plurality of first capacitor upper electrodes and said plurality of second capacitor upper electrodes 
     
     
         3 . The differential MOS capacitor semiconductor device as in  claim 2 , wherein said plurality of first capacitor upper electrodes and said plurality of second capacitor upper electrodes are arranged adjacent one another. 
     
     
         4 . The differential MOS capacitor semiconductor device as in  claim 1 , wherein said plurality of first capacitor upper electrodes and said plurality of second capacitor upper electrodes are arranged adjacent one another. 
     
     
         5 . The differential MOS capacitor semiconductor device as in  claim 4 , wherein said plurality of first capacitor upper electrodes comprise a duality of said first capacitor upper electrodes and said plurality of second capacitor upper electrodes comprise a duality of said second capacitor upper electrodes and wherein said first capacitor upper electrodes are juxtaposed and disposed adjacent said duality of second capacitor upper electrodes which are also juxtaposed. 
     
     
         6 . The differential MOS capacitor semiconductor device as in  claim 4 , wherein said first capacitor upper electrodes and said second capacitor upper electrodes are arranged sequentially adjacent one another along a first direction and one of said plurality of first capacitor upper electrodes is interposed between adjacent second capacitor upper electrodes of said plurality of second capacitor upper electrodes. 
     
     
         7 . The differential MOS capacitor semiconductor device as in  claim 1 , wherein:
 said substrate comprises a semiconductor substrate;   said conductive plate comprises an N-well formed in said substrate surface; and   no electrical components and no electrical connections to said conductive plate are disposed between said plurality of first capacitor upper electrodes and said plurality of second capacitor upper electrodes.   
     
     
         8 . The differential MOS capacitor semiconductor device as in  claim 1 , wherein said substrate comprises a semiconductor substrate and said conductive plate comprises an N-well formed in said semiconductor substrate. 
     
     
         9 . The differential MOS capacitor semiconductor device as in  claim 8 , wherein no electrical components are disposed within a convex polygonal region that includes said plurality of first capacitor upper electrodes and said plurality of second capacitor upper electrodes and further comprising a pickup device formed on said conductive plate laterally outside said convex polygonal region, said pickup device coupling said conductive plate to ground. 
     
     
         10 . The differential MOS capacitor semiconductor device as in  claim 9 , wherein said pickup device couples said conductive plate to ground through at least one electrical wire disposed over said conductive plate. 
     
     
         11 . The differential MOS capacitor semiconductor device as in  claim 1 , wherein said first gate is coupled to a first AC signal source and said second gate is coupled to a second AC signal source, wherein said first and second signal sources deliver signals that are out of phase. 
     
     
         12 . The differential MOS capacitor semiconductor device as in  claim 1 , wherein each said first capacitor upper electrode and each said second capacitor upper electrode is formed of polysilicon or a first metal layer of a plurality of metal layers, and
 further comprising a guard ring disposed in said substrate surface and at least partially surrounding said conductive plate.   
     
     
         13 . The differential MOS capacitor semiconductor device as in  claim 1 , wherein each of said first capacitor section and said second capacitor section is a variable capacitance MOS capacitor. 
     
     
         14 . The differential MOS capacitor semiconductor device as in  claim 1 , wherein each said first capacitor upper electrode and each said second capacitor upper electrode is formed of a plurality of stacked metal layers coupled together with vias. 
     
     
         15 . The differential MOS capacitor semiconductor device as in  claim 1 , wherein each of said first capacitor upper electrodes and second capacitor upper electrodes are disposed within a capacitor portion of said conductive plate, said capacitor portion having a convex polygonal shape, and wherein no further electrical components are disposed within said capacitor portion. 
     
     
         16 . A differential MOS capacitor semiconductor device comprising:
 a first capacitor section coupled to a first gate and including a plurality of first capacitor upper electrodes;   a second capacitor section coupled to a second gate and including a plurality of second capacitor upper electrodes; and   a conductive plate that serves as a common bottom capacitor plate for each of said first and second capacitor sections, is disposed in or on a substrate surface, and includes an enclosed capacitor region thereover, said enclosed capacitor region including said plurality of first capacitor upper electrodes and said plurality of second capacitor upper electrodes.   
     
     
         17 . The differential MOS capacitor semiconductor device as in  claim 16 , wherein said enclosed capacitor region is a convex polygon and includes no further electrical components therein. 
     
     
         18 . The differential MOS capacitor semiconductor device as in  claim 16 , wherein said substrate comprises a semiconductor substrate, no further electrical components are disposed within said enclosed capacitor region, said conductive plate comprises an N-well formed in said semiconductor substrate, and
 further comprising a pickup device formed on said conductive plate laterally outside said capacitor region, said pickup device coupling said conductive plate to ground.   
     
     
         19 . The differential MOS capacitor semiconductor device as in  claim 16 , wherein:
 said first gate is coupled to a first AC signal source and said second gate is coupled to a second AC signal source, said first and second signal sources delivering signals that are out of phase;   each said first and second capacitor upper electrode is formed of a plurality of stacked metal layers coupled together with vias; and   each of said first capacitor section and said second capacitor section is a variable capacitance MOS capacitor.   
     
     
         20 . A differential MOS capacitor semiconductor device comprising:
 a first capacitor section coupled to a first gate and including a plurality of first capacitor upper electrodes disposed over a common bottom capacitor plate;   a second capacitor section coupled to a second gate and including a plurality of second capacitor upper electrodes disposed over said common bottom capacitor plate;   said common bottom capacitor plate comprising a conductive plate disposed in a semiconductor substrate;   said first gate coupled to a first AC signal source; and   said second gate coupled to a second AC signal source,   wherein said first AC signal source delivers first signals that are in phase or out of phase with second signals delivered from said second AC signal source.   
     
     
         21 . The differential MOS capacitor semiconductor device as in  claim 20 , wherein no electrical components are interposed between said first capacitor upper electrodes of said plurality of first capacitor upper electrodes; no electrical components are interposed between said second capacitor upper electrodes of said plurality of second capacitor upper electrodes, and no electrical components are interposed between said plurality of first capacitor upper electrodes and said plurality of second capacitor upper electrodes. 
     
     
         22 . The differential MOS capacitor semiconductor device as in  claim 21 , wherein said first capacitor upper electrodes and said second capacitor upper electrodes are arranged sequentially adjacent one another along a first direction in a capacitor region that includes no further electrical components therein. 
     
     
         23 . The differential MOS capacitor semiconductor device as in  claim 20 , further comprising a guard ring disposed in said semiconductor substrate and at least partially surrounding said conductive plate, and wherein said first capacitor upper electrodes and said second capacitor upper electrodes each include a plurality of stacked metal layers.