Semiconductor device having a triple gate transistor and method for manufacturing the same

Abstract

In a semiconductor capable of reducing NBTI and a method for manufacturing the same, a multi-gate transistor includes an active region, gate dielectric, channels in the active region, and gate electrodes, and is formed on a semiconductor wafer. The active region has a top and side surfaces, and is oriented in a first direction. The gate dielectric is formed on the top and side surfaces of the active region. The channels are formed in the top and side surfaces of the active region. The gate electrodes are formed on the gate dielectric corresponding to the channels and aligned perpendicular to the active region such that current flows in the first direction. In one aspect of the invention, an SOI layer having a second orientation indicator in a second direction is formed on a supporting substrate having a first orientation indicator in a first direction.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a semiconductor wafer; and   a multi-gate transistor on the semiconductor wafer, the multi-gate transistor comprising:
 an active region extending in a first direction, and having a plurality of current-carrying surfaces including a current-carrying top surface and two current-carrying side surfaces; 
 a gate dielectric on the plurality of current-carrying surfaces; and 
 a gate electrode extending in a second direction different from the first direction on the gate dielectric, 
 wherein the first direction is a <100> crystal direction, and current flows along the first direction in the active region. 
   
     
     
         2 . The semiconductor device of  claim 1 , wherein at least two current-carrying surfaces among the plurality of current-carrying surfaces have the same crystal plane. 
     
     
         3 . The semiconductor device of  claim 2 , wherein the at least two current-carrying surfaces are formed in {100} crystal planes. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the multi-gate transistor further comprises:
 a top channel in the current-carrying top surface of the active region; and   side channels in the current-carrying side surfaces of the active region,   wherein at least two channels among the top and side channels are oriented in the <100> crystal direction.   
     
     
         5 . The semiconductor device of  claim 1 , wherein the gate electrode comprises a first gate electrode corresponding to the current-carrying top surface of the active region, and second and third gate electrodes corresponding to the current-carrying side surfaces of the active region. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the active region has at least one rounded corner. 
     
     
         7 . The semiconductor device of  claim 6 , wherein the at least one rounded corner is at an intersection of neighboring two current-carrying surfaces selected from the plurality of current-carrying surfaces. 
     
     
         8 . The semiconductor device of  claim 7 , wherein the radius of curvature at the intersection is at least 4.5 times the thickness of the gate dielectric. 
     
     
         9 . The semiconductor device as claimed in  claim 7 , wherein the radius of curvature at the intersection is at least 6 nm. 
     
     
         10 . The semiconductor device of  claim 1 , wherein the multi-gate transistor further comprises a plurality of channels in the plurality of current-carrying surfaces oriented in the <100> crystal direction. 
     
     
         11 . The semiconductor device of  claim 1 , wherein the active region has two rounded corners at intersections of the current-carrying top surface and the two current-carrying side surfaces. 
     
     
         12 . A semiconductor device comprising:
 a semiconductor wafer;   a shallow trench isolation region on the semiconductor wafer; and   a multi-gate transistor on the semiconductor wafer in proximity to the shallow trench isolation region, the multi-gate transistor comprising:
 an active region extending in a first direction, having a plurality of current-carrying surfaces including a current-carrying top surface and two current-carrying side surfaces, and having at least one rounded corner; 
 a gate dielectric on the plurality of current-carrying surfaces; and 
 a gate electrode extending in a second direction different from the first direction on the gate dielectric, 
 wherein the first direction is a <100> crystal direction, and current flows along the first direction in the active region. 
   
     
     
         13 . The semiconductor device of  claim 12 , wherein at least two current-carrying surfaces among the plurality of current-carrying surfaces have the same crystal plane. 
     
     
         14 . The semiconductor device of  claim 13 , wherein the at least two current-carrying surfaces are formed in {100} crystal planes. 
     
     
         15 . The semiconductor device of  claim 12 , wherein the multi-gate transistor further comprising:
 a top channel in the current-carrying top surface of the active region; and   side channels in the current-carrying side surfaces of the active region,   wherein at least two channels among the top and side channels are oriented in the <100> crystal direction.   
     
     
         16 . The semiconductor device of  claim 12 , wherein the gate electrode comprises a first gate electrode corresponding to the current-carrying top surface of the active region, and second and third gate electrodes corresponding to the current-carrying side surfaces of the active region, the second and third gate electrodes being disposed on the shallow trench isolation region. 
     
     
         17 . The semiconductor device of  claim 12 , wherein the semiconductor wafer comprises an orientation indicator that indicates a <110> crystal direction, and wherein the active region is aligned at 45 degrees with respect to the orientation indicator. 
     
     
         18 . The semiconductor device of  claim 12 , wherein the at least one rounded corner is at an intersection of neighboring two current-carrying surfaces selected from the plurality of current-carrying surfaces. 
     
     
         19 . The semiconductor device of  claim 12 , wherein the multi-gate transistor further comprises a plurality of channels in the plurality of current-carrying surfaces oriented in the <100> crystal direction. 
     
     
         20 . The semiconductor device of  claim 12 , wherein the at least one rounded corner includes two rounded corners at intersections of the current-carrying top surface and the two current-carrying side surfaces.