Semiconductor devices and processing methods

Abstract

Various embodiments provide a semiconductor device, including a final metal layer having a top side and at least one sidewall; and a passivation layer disposed over at least part of at least one of the top side and the at least one sidewall of the final metal layer; wherein the passivation layer has a substantially uniform thickness.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a final metal layer, comprising a top side and at least one sidewall;   a passivation layer disposed over at least part of at least one of the top side and the at least one sidewall of the final metal layer;   wherein the passivation layer has a substantially uniform thickness.   
     
     
         2 . The semiconductor device according to  claim 1 ,
 wherein the passivation layer is disposed over the top side and the at least one sidewall of the final metal layer.   
     
     
         3 . The semiconductor device according to  claim 1 ,
 wherein the passivation layer encapsulates the final metal layer.   
     
     
         4 . The semiconductor device according to  claim 1 ,
 wherein the thickness of the passivation layer is less than or equal to about 100 nm.   
     
     
         5 . The semiconductor device according to  claim 1 ,
 wherein the passivation layer comprises a metal oxide.   
     
     
         6 . The semiconductor device according to  claim 5 ,
 wherein the metal oxide is an oxide, which is different from a native oxide of the material of the final metal layer.   
     
     
         7 . The semiconductor device according to  claim 1 ,
 wherein the passivation layer comprises aluminum oxide.   
     
     
         8 . The semiconductor device according to  claim 1 ,
 wherein the final metal layer comprises at least one metal from the following group of metals, the group of metals consisting of: copper, silver, palladium, silver, tungsten, aluminum and tin.   
     
     
         9 . The semiconductor device according to  claim 1 ,
 wherein the final metal layer comprises copper.   
     
     
         10 . The semiconductor device according to  claim 1 ,
 wherein the passivation layer is a first passivation layer, and   the semiconductor device further comprising   a second passivation layer at least partially surrounding the first passivation layer.   
     
     
         11 . The semiconductor device according to  claim 10 ,
 wherein the second passivation layer comprises at least one material from the following group of materials, the group of materials consisting of: polyimide, epoxy, polymer, silicon dioxide, silicon nitride, silicon oxinitride.   
     
     
         12 . The semiconductor device according to  claim 10 , further comprising
 a hole formed through at least one of the first passivation layer and the second passivation layer.   
     
     
         13 . The semiconductor device according to  claim 12 , further comprising
 an interconnect structure formed through the hole and electrically connected to the final metal layer.   
     
     
         14 . The semiconductor device according to  claim 13 ,
 wherein the interconnect structure comprises an electrically conductive wire.   
     
     
         15 . The semiconductor device according to  claim 13 ,
 wherein the hole is formed through the first passivation layer and the second passivation layer; and   wherein the interconnect structure is electrically connected to the final metal layer through the hole formed through the first passivation layer and the second passivation layer.   
     
     
         16 . The semiconductor device according to  claim 13 ,
 wherein the hole is formed through the second passivation layer but not through the first passivation layer; and   wherein the interconnect structure is electrically connected to the final metal layer via the first passivation layer.   
     
     
         17 . A method for processing a semiconductor device, comprising:
 forming a final metal layer having a top side and at least one sidewall;   forming a passivation layer over at least part of at least one of the top side and the at least one sidewall of the final metal layer by means of an atomic layer deposition process.   
     
     
         18 . The method according to  claim 17 ,
 wherein forming the passivation layer over at least part of at least one of the top side and the at least one sidewall of the final metal layer comprises   conformally forming the passivation layer over the top side and the at least one sidewall of the final metal layer.   
     
     
         19 . The method according to  claim 17 ,
 wherein forming the passivation layer over at least part of at least one of the top side and the at least one sidewall of the final metal layer comprises   encapsulating the final metal layer with the passivation layer.   
     
     
         20 . The method according to  claim 17 ,
 wherein the passivation layer comprises a metal oxide.   
     
     
         21 . The method according to  claim 20 ,
 wherein the metal oxide is an oxide, which is different from a native oxide of the material of the final metal layer.   
     
     
         22 . The method according to  claim 17 ,
 wherein the passivation layer comprises aluminum oxide.   
     
     
         23 . The method according to  claim 17 ,
 wherein the atomic layer deposition process comprises an aluminum precursor comprising trimethylaluminum.   
     
     
         24 . The method according to  claim 17 ,
 wherein the atomic layer deposition process comprises at least one oxidizing precursor from the following group of oxidizing precursors, the group of oxidizing precursors consisting of: water, alcohol, isopropanol, ethanol and methanol.   
     
     
         25 . The method according to  claim 17 ,
 wherein the final metal layer comprises at least one metal from the following group of metals, the group of metals consisting of: copper, silver, palladium, silver, tungsten, aluminum and tin.   
     
     
         26 . The method according to  claim 17 ,
 wherein the passivation layer is a first passivation layer, and   the method further comprising   at least partially surrounding the passivation layer with a second passivation layer.   
     
     
         27 . The method according to  claim 26 ,
 wherein the second passivation layer comprises at least one material from the following group of materials, the group of materials consisting of: polyimide, epoxy, polymer, silicon dioxide, silicon nitride, silicon oxinitride.   
     
     
         28 . The method according to  claim 26 , further comprising
 forming a hole through at least one of the first passivation layer and the second passivation layer;   forming an interconnect structure through the hole; and   electrically connecting the interconnect structure to the final metal layer.   
     
     
         29 . The method of  claim 28 ,
 wherein forming a hole through at least one of the first passivation layer and the second passivation layer comprises   forming the hole through the first passivation layer and the second passivation layer; and   wherein electrically connecting the interconnect structure to the final metal layer comprises   electrically connecting the interconnect structure to the final metal layer through the hole.   
     
     
         30 . The method of  claim 28 ,
 wherein forming a hole through at least one of the first passivation layer and the second passivation layer comprises   forming the hole through the second passivation layer but not through the first passivation layer; and   wherein electrically connecting the interconnect structure to the final metal layer comprises   electrically connecting the interconnect structure to the final metal layer through the hole and via the first passivation layer.   
     
     
         31 . A metallization structure arrangement, comprising
 a semiconductor carrier comprising a metallization structure formed over a surface of the semiconductor carrier; and   a layer comprising aluminum oxide disposed over at least a part of the metallization structure.   
     
     
         32 . The metallization structure arrangement according to  claim 31 , further comprising a passivation layer at least partially surrounding the layer comprising aluminum oxide. 
     
     
         33 . The metallization structure arrangement according to  claim 31 ,
 wherein the semiconductor carrier comprises a semiconductor chip.   
     
     
         34 . The metallization structure arrangement according to  claim 33 ,
 wherein the surface is a top surface of the semiconductor chip.   
     
     
         35 . The metallization structure arrangement according to  claim 33 ,
 wherein the surface is a bottom surface of the semiconductor chip.   
     
     
         36 . The metallization structure arrangement according to  claim 31 ,
 wherein the layer comprising aluminum oxide is formed conformally over at least one surface of the metallization structure.   
     
     
         37 . The metallization structure arrangement according to  claim 31 ,
 wherein the layer comprising aluminum oxide encapsulates the metallization structure.   
     
     
         38 . The metallization structure arrangement according to  claim 31 ,
 wherein the layer comprising aluminum oxide has a thickness of less than or equal to about 100 nm.   
     
     
         39 . The metallization structure arrangement according to  claim 31 ,
 wherein the metallization structure comprises a metal contact pad.   
     
     
         40 . The metallization structure arrangement according to  claim 31 ,
 wherein the metallization structure comprises a top surface and one or more side walls,   wherein the layer comprising aluminum oxide covers at least one of the top surface and the one or more side walls.   
     
     
         41 . The metallization structure arrangement according to  claim 32 ,
 wherein the passivation layer comprises at least one material from the following group of materials, the group of materials consisting of: polyimide, epoxy, polymer, silicon dioxide, silicon nitride, silicon oxinitride.   
     
     
         42 . The metallization structure arrangement according to  claim 32 , further comprising an interconnect structure formed through a hole in at least one of the passivation layer and the layer comprising aluminum oxide, wherein the interconnect structure is electrically connected to the metallization structure. 
     
     
         43 . The metallization structure arrangement according to  claim 42 ,
 wherein the interconnect structure comprises an electrically conductive wire.   
     
     
         44 . The metallization structure arrangement according to  claim 42 ,
 wherein the interconnect structure comprises a wire bond structure wherein the wire bond structure is bonded to the metallization structure.   
     
     
         45 . The metallization structure arrangement according to  claim 44 ,
 wherein the wire bond structure comprises at least one of a ball bond and a wedge bond.   
     
     
         46 . The metallization structure arrangement according to  claim 42 ,
 wherein the interconnect structure is electrically connected to the metallization structure through a hole formed through the passivation layer and the layer comprising aluminum oxide.   
     
     
         47 . The metallization structure arrangement according to  claim 32 ,
 wherein the passivation layer comprises a hole over the layer comprising aluminum oxide, wherein the interconnect structure is electrically connected to the metallization structure via the layer comprising aluminum oxide.   
     
     
         48 . The metallization structure arrangement according to  claim 31 ,
 wherein the metallization structure comprises at least one metal from the following group of metals, the group of metals consisting of: copper, silver, palladium, silver, tungsten, aluminum and tin.   
     
     
         49 . The metallization structure arrangement according to  claim 31 ,
 wherein the metallization structure comprises copper.   
     
     
         50 . The metallization structure arrangement according to  claim 31 ,
 wherein the metallization structure comprises aluminum.   
     
     
         51 . A semiconductor chip arrangement, comprising
 a semiconductor chip comprising a metallization structure formed over a surface of the semiconductor chip;   an aluminum oxide layer and a passivation layer disposed at least partially over the metallization structure.   
     
     
         52 . The semiconductor chip structure arrangement according to  claim 51 ,
 wherein the aluminum oxide layer covers a top surface and one or more side walls of the metallization structure.   
     
     
         53 . The semiconductor chip structure arrangement according to  claim 51 ,
 wherein the aluminum oxide layer is formed conformally over at least one surface of the metallization structure.   
     
     
         54 . The semiconductor chip structure arrangement according to  claim 51 ,
 wherein the aluminum oxide layer is arranged such that at least one of contamination and corrosion at a surface of the metallization structure is prevented.   
     
     
         55 . The semiconductor chip structure arrangement according to  claim 51 ,
 wherein the aluminum oxide layer is arranged such that growth of additional structures from the metallization structure is prevented.   
     
     
         56 . A method for manufacturing a metallization structure arrangement, the method comprising
 disposing a layer comprising aluminum oxide over a metallization structure, the metallization structure being disposed over a surface of a semiconductor carrier.   
     
     
         57 . The method according to  claim 56 ,
 further comprising at least partially surrounding the layer comprising aluminum oxide with a passivation layer.   
     
     
         58 . The method according to  claim 56 ,
 wherein disposing a layer comprising aluminum oxide over a metallization structure comprises covering at least one of a top surface and one or more side walls of the metallization structure with aluminum oxide.   
     
     
         59 . The method according to  claim 56 ,
 wherein disposing a layer comprising aluminum oxide over a metallization structure comprises disposing the layer comprising aluminum oxide by an atomic layer deposition process.   
     
     
         60 . The method according to  claim 59 ,
 wherein disposing the layer comprising aluminum oxide by atomic layer deposition comprises forming the layer comprising aluminum oxide conformally over at least one surface of the metallization structure.   
     
     
         61 . The method according to  claim 56 ,
 wherein disposing an aluminum oxide layer over a metal pad of a chip comprises forming a chemical reaction at at least one surface of the metallization structure to remove metal oxides from the metallization structure.   
     
     
         62 . The method according to  claim 57 , further comprising
 forming a hole through at least one of the passivation layer and the layer comprising aluminum oxide; and   forming an interconnect structure through the hole thereby electrically connecting the interconnect structure to the metallization structure.   
     
     
         63 . The method according to  claim 59 ,
 wherein the atomic layer deposition process comprises an aluminum precursor comprising trimethylaluminum.   
     
     
         64 . The method according to  claim 59 ,
 wherein the atomic layer deposition process comprises at least one oxidizing precursor from the following group of oxidizing precursors, the group of oxidizing precursors consisting of: water, alcohol, isopropanol, ethanol and methanol.