Raid configuration in a flash memory data storage device

Abstract

A method of storing data in a flash memory data storage device that includes a plurality of memory chips is disclosed. The method includes determining a number of memory chips in the data storage device, defining, via a host coupled to the data storage device, a first partition of the data storage device, where the first partition includes a first subset of the plurality of memory chips and defining a second partition of the data storage device via a host coupled to the data storage device, where the second partition includes a second subset of the plurality of memory chips. First data is written to the first partition while reading data from the second partition, and first data is written to the second partition while reading data from the first partition.

1 - 23 . (canceled) 
     
     
         24 . A method comprising:
 transmitting, from a data storage device to a host device via an interface, information indicating a number of flash memory chips in the data storage device, a first portion of the flash memory chips being implemented in a first memory channel and a second portion of the flash memory chips being implemented in a second memory channel;   defining, by the host, a first data storage partition of the data storage device, the first data storage partition including a first subset of the flash memory chips, the first subset having one or more flash memory chips of the first memory channel and one or more flash memory chips of the second memory channel;   defining, by the host, a second data storage partition of the data storage device, the second data storage partition including a second subset of the flash memory chips that does not include any flash memory chips of the first subset, a boundary between the first partition and second partition being defined by the first subset of the flash memory chips and the second subset of the flash memory chips;   providing, via the interface, first data from the host to the data storage device;   writing the first data to the first partition while reading data from the second partition; and   writing the first data to the second partition while reading data from the first partition.   
     
     
         25 . That method of  claim 24 , wherein the interface includes a PCIe interface. 
     
     
         26 . The method of  claim 24 , further comprising:
 providing, via the interface, second data from the host device to the data storage device;   writing second data to the first partition, while reading data from the second partition;   writing the second data to the second partition while reading data from the first partition; and   for N=3rd to at least 10th:
 providing, via the interface, N data from the host to the data storage device; 
 writing the N data to the first partition while reading data from the second partition; and 
 writing the N data to the second partition while reading data from the first partition. 
   
     
     
         27 . The method of  claim 24 , wherein the transmitted information includes information about a physical architecture of the data storage device, including information about connections between particular flash memory chips and particular channels of the data storage device. 
     
     
         28 . The method of  claim 24 , further comprising determining, by the host, an address location in the data storage device to which to write data from the host, the address location specifying that the data from the host be written to a specific one of the flash memory chips. 
     
     
         29 . The method of  claim 24 , further comprising:
 determining a number of physical channels for communication of data between the host and the flash memory chips, each physical channel being operably connected to a different plurality of the flash memory chips;   determining a first subset of the physical channels, wherein physical channels of the first subset of physical channels are operably connected only to flash memory chips of the first subset of the flash memory chips; and   determining a second subset of the physical channels, wherein physical channels of the second subset of physical channels are operably connected only to flash memory chips of the second subset of the flash memory chips.   
     
     
         30 . The method of  claim 24 , further comprising:
 receiving, via the interface, an indication from the data storage device to the host that a flash memory chip of the first partition has failed or is likely to fail;   re-defining, by the host, the first partition of the data storage device to include a third subset of the flash memory chips,   the third subset of the flash memory chips being different from the first subset of the flash memory chips, and   the third subset of the flash memory chips not including any flash memory chips of the second subset.   
     
     
         31 . The method of  claim 30 , wherein re-defining the first partition includes defining the third subset of the flash memory chips as the first subset of the flash memory chips but for the flash memory chip that has failed or that is approaching failure. 
     
     
         32 . An apparatus comprising:
 a flash memory data storage device including a plurality of flash memory chips, a first portion of the plurality of flash memory chips being implemented in a first memory channel and a second portion of the plurality of flash memory chips being implemented in a second memory channel;   an interface; and   a host operably coupled to the data storage device via the interface, the host comprising:
 a configuration detection engine configured to determine, by communicating with the data storage device over the interface, a number of flash memory chips in the data storage device; 
 a partition engine configured to define a first partition of the data storage device and a second partition of the data storage device, the first partition including a first subset of the plurality of flash memory chips having one or more flash memory chips of the first memory channel and one or more flash memory chips of the second memory channel, the second partition including a second subset of the plurality of flash memory chips that does not include any flash memory chips of the first subset of the plurality of flash memory chips, a boundary between the first partition and the second partition being defined by the first subset of the plurality of flash memory chips and the second subset of the plurality flash memory chips. 
   
     
     
         33 . The apparatus of  claim 32 , wherein:
 the driver is further configured to transmit second data to the data storage device; and   the data storage device is configured to:
 write the second data to the first partition while reading data from the second partition; and 
 write the second data to the second partition while reading data from the first partition. 
   
     
     
         34 . The apparatus of  claim 32 , wherein the data storage device is configured to transmit, via the interface upon receiving a command from the host, information from the data storage device to the host indicating the number of flash memory chips in the data storage device. 
     
     
         35 . The apparatus of  claim 34 , wherein the transmitted information includes information about physical architecture of the data storage device, including information about connections between particular flash memory chips and particular channels of the data storage device. 
     
     
         36 . The apparatus of  claim 32 , wherein the host further comprises an address assignment engine configured to assign a memory address to data to be written to the data storage device, wherein the assigned memory address specifies that the data be written is to a specific one of the plurality of flash memory chips. 
     
     
         37 . The apparatus of  claim 32 , wherein:
 the configuration detection engine is further configured, by communication with the data storage device via the interface, to detect a number of physical channels of the data storage device; and   the partition engine is further configured to:
 determine a first subset of the number of physical channels, channels of the first subset of physical channels being operably connected only to flash memory chips of the first subset of the plurality of flash memory chips; and 
 determine a second subset of the number of physical channels, channels of the second subset of physical channels being operably connected only to flash memory chips of the second subset of the plurality of flash memory chips. 
   
     
     
         38 . The apparatus of  claim 32 , wherein the second partition only includes flash memory chips that are operably connected to the second memory channel. 
     
     
         39 . The apparatus of  claim 32 , wherein the partition engine is further configured to:
 receive, via the interface, an indication from the data storage device that a flash memory chip of the first partition has failed or is likely to fail; and   re-define the first partition of the data storage device to include a third subset of the plurality of flash memory chips, the third subset of the plurality of flash memory chips being different from the first subset of the plurality of flash memory chips and not including any flash memory chips of the second subset.   
     
     
         40 . The apparatus of  claim 39 , wherein re-defining the first partition to include the third subset of the plurality of flash memory chips includes defining the third subset as the first subset of the plurality of flash memory chips but for the flash memory chip that has failed or that is approaching failure. 
     
     
         41 . The apparatus of  claim 32 , wherein the interface includes a PCIe interface. 
     
     
         42 . The apparatus of  claim 41 , wherein the PCIe interface includes a PCIe x4 interface. 
     
     
         43 . The apparatus of  claim 41 , wherein the PCIe interface includes a PCIe x8 interface.