Inter-memory data transfer control unit

Abstract

A data transfer device that transfers data to a memory according to an instruction from a processor via a bus through which a response indicating completion of data writing in the memory is not sent back, comprises an inter-memory data transfer control unit including an operation start trigger receiving unit, a parameter acquiring unit, a read unit, and a write unit. When the write unit detects switching of a write destination memory, the write unit confirms write completion as to the memory by a procedure different from writing. When a data transfer instructed by the processor is completed, the write unit confirms write completion as to the write destination memory at the end of the data transfer by the procedure different from writing. The inter-memory data transfer control unit notifies the processor of completion of an inter-memory data transfer based on the confirmation of the write completion.

What is claimed is: 
     
         1 . An inter-memory data transfer control unit transferring data from a first memory to a second memory, comprising:
 an operation start trigger receiving unit for receiving an operation start trigger from a processor;   a parameter acquiring unit for acquiring a transfer instruction parameter created by the processor;   a read unit for reading data from the first memory designated by the transfer instruction parameter;   a write unit for writing the data read by the read unit into the second memory designated by the transfer instruction parameter,   wherein   when a data transfer instructed by the processor is completed, in order to confirm that the data written into the second memory is completed, the write unit performs confirmation of write completion as to the second memory at the end of the data transfer by the procedure different from writing into the second memory, and   the inter-memory data transfer control unit notifies the processor of completion of an inter-memory data transfer based on the confirmation of the write completion.   
     
     
         2 . The inter-memory data transfer control unit according to  claim 1 , wherein in order to confirm that writing into the second memory is completed, the write unit of the inter-memory data transfer control unit performs reading from the first memory through the same bus as used in writing into the second memory as the procedure different from writing into the second memory. 
     
     
         3 . The inter-memory data transfer control unit according to  claim 1 , wherein in order to confirm that writing into the second memory is completed, the write unit of the inter-memory data transfer control unit performs access to a register in a memory controller through the same bus as used in writing into the second memory as the procedure different from writing into the second memory. 
     
     
         4 . The inter-memory data transfer control unit according to  claim 3 , wherein the memory controller is enabled to refer to at least one register provided in the memory controller for at least a number of times of writing by the memory controller. 
     
     
         5 . The inter-memory data transfer control unit according to  claim 4 , wherein in order to confirm that writing into the second memory is completed, the inter-memory data transfer control unit performs reading from the register enabled to referring for the number of times of writing by the memory controller through the same bus as used in writing into the second memory as the procedure different from writing into the second memory, and
 the inter-memory data transfer control unit compares a value read from the register with the number of times of writing by the inter-memory data transfer control unit and confirms whether the data transfer is normally performed.   
     
     
         6 . The inter-memory data transfer control unit according to  claim 1 , wherein in order to confirm that writing into the second memory is completed, the inter-memory data transfer control unit includes a write completion confirmation request/response processing unit for processing a write completion confirmation request dedicated to requesting for securing writing and a write completion confirmation response for response to the write completion confirmation request as the procedure different from writing into the second memory,
 the inter-memory data transfer control unit confirms completion of the writing by sending the write completion confirmation request and receiving the write completion confirmation response.   
     
     
         7 . The inter-memory data transfer control unit according to  claim 1 , wherein the inter-memory data transfer control unit includes a signal line between the inter-memory data transfer control unit and a memory controller for confirmation of securing writing and for response to the confirmation request, in order to confirm that writing into the second memory is completed, as the procedure different from writing into the second memory, the inter-memory data transfer control unit sends a signal for requesting confirmation of securing writing to the memory controller,
 the inter-memory data transfer control unit receives a signal of completion of securing writing that the memory controller having received the signal for requesting confirmation of securing writing sent to a request source as a response to the request for confirmation of securing writing when the memory controller detects completion of a requested writing, and   the inter-memory data transfer control unit confirms completion of writing by receiving the signal of completion of securing writing.   
     
     
         8 . The inter-memory data transfer control unit according to  claim 1 , wherein
 the inter-memory data transfer control unit detects a timing of switching of the write destination memory from the first memory to the second memory by switching of an access destination memory controller.   
     
     
         9 . The inter-memory data transfer control unit according to  claim 1 , wherein
 the inter-memory data transfer control unit determines a timing of switching of the write destination memory from the first memory to the second memory with reference to an access destination address of the memory.   
     
     
         10 . The inter-memory data transfer control unit according to  claim 9 , wherein
 the inter-memory data transfer control unit determines a timing of switching of the write destination memory from the first memory to the second memory by the memory controller.   
     
     
         11 . The inter-memory data transfer control unit according to  claim 9 , wherein
 the inter-memory data transfer control unit determines a timing of switching of the write destination memory from the first memory to the second memory by a DIMM of the second memory.   
     
     
         12 . The inter-memory data transfer control unit according to  claim 9 , wherein
 the inter-memory data transfer control unit determines a timing of switching of the write destination memory from the first memory to the second memory by a bank of the memory.   
     
     
         13 . The inter-memory data transfer control unit according to  claim 1 , wherein
 the transfer instruction parameter includes at least, as the information on a data transfer instruction,   a start address of a transfer source memory,   at least one start address of a transfer destination memory,   necessity information on whether or not check of completion of writing to each transfer destination memory, and   a transfer data length,   when the write unit detects switching of the write destination memory from the first memory to the second memory, in order to confirm that writing into the first memory is completed, the write unit determines whether or not performing confirmation of write completion as to the first memory based on the necessity information in the transfer instruction parameter,   when the write unit determines that the confirmation of write completion is required, the write unit performs confirmation of write completion as to the first memory by the procedure different from writing into the second memory,   when a data transfer instructed by the processor is completed, in order to confirm that writing into the second memory is completed as to the write destination memory at the end of the data transfer, the write unit determines whether or not performing confirmation of write completion as to the write destination memory based on the necessity information in the transfer instruction parameter, and   when the write unit determines that the confirmation of write completion is required, the write unit performs confirmation of write completion as to the write destination memory at the end of the data transfer by the procedure different from writing into the second memory.   
     
     
         14 . The inter-memory data transfer control unit according to  claim 1 , wherein
 the inter-memory data transfer control unit includes two different-operation start trigger receiving units,   if the inter-memory data transfer control unit is started by receiving the operation start trigger from one of the operation start trigger receiving units, when the inter-memory data transfer control unit detects switching of a write destination memory from the first memory to the second memory, in order to confirm that writing into the first memory is completed, the inter-memory data transfer control unit performs confirmation of write completion as to the first memory by the procedure different from writing into the second memory,   when a data transfer instructed by the processor is completed, in order to confirm that writing into the second memory is completed as to the write destination memory at the end of the data transfer, the inter-memory data transfer control unit performs confirmation of write completion as to the write destination memory at the end of the data transfer by the procedure different from writing into the second memory, and   the inter-memory data transfer control unit notifies the processor of completion of an inter-memory data transfer based on the confirmation of write completion;   if the inter-memory data transfer control unit is started by receiving the operation start trigger from the other one of the operation start trigger receiving units, the inter-memory data transfer control unit omits performing confirmation of write completion as to the write destination memory, and   the inter-memory data transfer control unit notifies the processor of completion of the inter-memory data transfer.   
     
     
         15 . The inter-memory data transfer control unit of  claim 1 , wherein the inter-memory data transfer control unit is a direct memory access.