Isolation components for transistors formed on fin features of semiconductor substrates

Abstract

In an embodiment, an apparatus includes a substrate including a surface having a planar portion and a fin feature extending in a direction substantially perpendicular to the planar portion and having a thickness less than a thickness of the substrate. The apparatus also includes a first transistor that includes a first gate region formed over the fin feature, a first source region formed from a body of the fin feature, and a first drain region formed from the body of the fin feature. Additionally, the apparatus includes a second transistor that includes a second gate region formed over the fin feature, a second source region formed from the body of the fin feature, and a second drain region formed from the body of the fin feature. Further, the apparatus includes an isolation component formed between the first transistor and the second transistor, where the isolation component has a width less than 30 nm.

What is claimed is: 
     
         1 . An apparatus comprising:
 a substrate including a surface, wherein the surface includes
 a planar portion, and 
 a fin feature extending in a direction substantially perpendicular to the planar portion and having a thickness less than a thickness of the substrate; 
   a first transistor, wherein the first transistor includes
 a first gate region formed over the fin feature, 
 a first source region formed from a body of the fin feature, and 
 a first drain region formed from the body of the fin feature; 
   a second transistor, wherein the second transistor includes
 a second gate region formed over the fin feature, 
 a second source region formed from the body of the fin feature, and 
 a second drain region formed from the body of the fin feature; and 
   an isolation component formed between the first transistor and the second transistor, wherein the isolation component has a width less than 30 nm.   
     
     
         2 . The apparatus of  claim 1 , wherein:
 the fin feature has a substantially rectangular shape;   the fin feature includes four sides extending in the direction substantially perpendicular to the planar portion; and   the fin feature includes an additional side substantially parallel to the planar portion.   
     
     
         3 . The apparatus of  claim 1 , wherein:
 the first drain region of the first transistor is adjacent to the isolation component; and   the second source region of the second transistor is adjacent to the isolation component.   
     
     
         4 . The apparatus of  claim 1 , wherein the width of the isolation component is in a range of 9 nm to 18 nm. 
     
     
         5 . The apparatus of  claim 1 , wherein:
 a layer is disposed on the planar portion of the surface of the substrate;   the layer includes a first dielectric material; and   the isolation component includes a second dielectric material.   
     
     
         6 . An apparatus comprising:
 a substrate including a surface, wherein the surface includes
 a planar portion, and 
 a fin feature extending in a direction substantially perpendicular to the planar portion and having a thickness less than a thickness of the substrate; 
   a layer formed over the planar portion of the surface of the substrate, wherein the layer includes a first dielectric material;   a first transistor, wherein the first transistor includes
 a first gate region disposed on at least two sides of the fin feature, 
 a first source region formed from a body of the fin feature, and 
 a first drain region formed from the body of the fin feature; 
   a second transistor, wherein the second transistor includes
 a second gate region formed on the at least two sides of the fin feature, 
 a second source region formed from the body of the fin feature, and 
 a second drain region formed from the body of the fin feature; and 
   an isolation component formed between the first transistor and the second transistor, wherein the isolation component includes a second dielectric material that is different from the first dielectric material.   
     
     
         7 . The apparatus of  claim 6 , wherein the first dielectric material has a dielectric constant with a value greater than a value of the dielectric constant of the second material. 
     
     
         8 . The apparatus of  claim 6 , wherein the first dielectric material includes one of SiO 2  or SiN. 
     
     
         9 . The apparatus of  claim 6 , wherein the isolation component includes a third dielectric material that is different from (i) the first dielectric material and (ii) the second dielectric material. 
     
     
         10 . The apparatus of  claim 9 , wherein:
 the isolation component includes a cavity filled with the third dielectric material; and   the cavity is encased by at least the second dielectric material.   
     
     
         11 . The apparatus of  claim 6 , wherein the isolation component has a width in a range of 6 nm to 29 nm. 
     
     
         12 . The apparatus of  claim 6 , wherein the substrate includes an additional fin feature, and wherein the substrate further includes:
 a third transistor, wherein the third transistor includes
 a third gate region disposed on at least two sides of the additional fin feature, 
 a third source region formed from a body of the additional fin feature, and 
 a third drain region formed from the body of the fin feature; 
   a fourth transistor, wherein the fourth transistor includes
 a fourth gate region disposed on the at least two sides of the additional fin feature, 
 a fourth source region formed from the body of the additional fin feature, and 
 a fourth drain region formed from the body of the additional fin feature; and 
   an additional isolation component formed between the third transistor and the fourth transistor.   
     
     
         13 . A method comprising:
 forming a fin feature on a portion of a surface of a substrate including silicon, wherein the fin feature extends in a direction perpendicular to a planar portion of the surface of the substrate;   forming a first region of polycrystalline silicon over a first portion of the fin feature of the substrate;   forming a second region of polycrystalline silicon over a second portion of the fin feature of the substrate;   forming a third region of polycrystalline silicon over a third portion of the fin feature of the substrate, wherein the third region of polycrystalline silicon is disposed between (i) the first region of polycrystalline silicon and (ii) the second region of polycrystalline silicon;   forming a first spacer region between (i) the first region of polycrystalline silicon and (ii) the third region of polycrystalline silicon, wherein the first spacer region includes a first dielectric material;   forming a second spacer region between (i) the second region of polycrystalline silicon and (ii) the third region of polycrystalline silicon, wherein the second spacer region includes the first dielectric material;   removing at least (i) the third region of polycrystalline silicon and (ii) at least a portion of the fin feature formed under the third region of polycrystalline silicon to thereby form a gap between (i) the first region of polycrystalline silicon and (ii) the second region of polycrystalline silicon; and   disposing a second dielectric material into the gap between (i) the first region of polycrystalline silicon and (ii) the second region of polycrystalline silicon to form an isolation component.   
     
     
         14 . The method of  claim 13 , further comprising:
 placing a mask over the substrate, wherein the mask includes an opening corresponding to a location of the third region of polycrystalline silicon; and   etching (i) the third region of polycrystalline silicon and (ii) the at least a portion of fin feature according to a pattern of the mask.   
     
     
         15 . The method of  claim 14 , further comprising etching a portion of the substrate such that the gap extends below a surface of the planar portion of the surface of the substrate. 
     
     
         16 . The method of  claim 13 , further comprising:
 forming an additional fin feature on the substrate,   wherein both (i) the fin feature and (ii) the additional fin feature are formed using a self-aligning double patterning process.   
     
     
         17 . The method of  claim 13 , wherein a width of the isolation component is less than 30 nm. 
     
     
         18 . The method of  claim 13 , wherein the first dielectric material is different from the second dielectric material. 
     
     
         19 . The method of  claim 13 , wherein:
 the first polycrystalline silicon region forms a gate of a first transistor; and   the third polycrystalline silicon region forms a gate of a second transistor.   
     
     
         20 . The method of  claim 13 , further comprising:
 after forming the first spacer region and the second spacer region, embedding stressor materials into the substrate, wherein the stressor materials include one or both of SiGe and/or SiC.