Semiconductor device

Abstract

A semiconductor device comprises a vertical MOS transistor including a semiconductor substrate having a silicon pillar, a gate electrode formed along a sidewall of the silicon pillar, a gate insulating film formed between the gate electrode and the silicon pillar, an upper diffusion layer formed on the top of the silicon pillar, and a lower diffusion layer formed lower than the upper diffusion layer in the semiconductor substrate; and a pad electrically connected to the lower diffusion layer. Breakdown occurs between the lower diffusion layer and the semiconductor substrate when a surge voltage is applied.

What is claimed is: 
     
         1 . A semiconductor device, comprising a vertical MOS transistor including: an upper diffusion layer and a lower diffusion layer which is located lower than said upper diffusion layer, as source and drain electrodes, wherein
 breakdown occurs between said lower diffusion layer and a semiconductor substrate in which said lower diffusion layer is formed when a surge voltage is applied.   
     
     
         2 . The semiconductor device as defined in  claim 1 , wherein
 said vertical MOS transistor operates as a first electrostatic discharge protection device and protects said semiconductor device by discharging said surge voltage by means of said breakdown.   
     
     
         3 . The semiconductor device as defined in  claim 2 , further comprising a second electrostatic discharge protection device; wherein
 said vertical MOS transistor is a trigger transistor that serves to start an operation of said second electrostatic discharge protection device.   
     
     
         4 . The semiconductor device as defined in  claim 3 , further comprising an element isolation region in said semiconductor substrate; wherein
 said second electrostatic discharge protection device comprises a bipolar transistor; and   at least one of diffusion layers of said bipolar transistor is disposed horizontally adjacent to said lower diffusion layer of said vertical MOS transistor via said element isolation region.   
     
     
         5 . The semiconductor device as defined in  claim 3 , further comprising an element isolation region in said semiconductor substrate; wherein
 said second electrostatic discharge protection device comprises a thyristor transistor; and   at least one of diffusion layers of said thyristor transistor is disposed horizontally adjacent to said lower diffusion layer of said vertical MOS transistor via said element isolation region.   
     
     
         6 . The semiconductor device as defined in  claim 1 , further comprising a transistor to be protected by said vertical MOS transistor which operates as an electrostatic discharge protection device; wherein
 said vertical MOS transistor is disposed between said pad and said transistor to be protected.   
     
     
         7 . The semiconductor device as defined in  claim 1 , wherein
 said semiconductor substrate is connected to a fixed potential.   
     
     
         8 . A semiconductor device, comprising:
 a semiconductor substrate;   a vertical MOS transistor including a gate electrode formed on said semiconductor substrate, an upper diffusion layer formed on said semiconductor substrate on an upper end side of said gate electrode as one of source and drain electrodes, and a lower diffusion layer formed in said semiconductor substrate on a lower end side of said gate electrode as the other of said source and drain electrodes; and   a pad electrically connected to said lower diffusion layer; wherein   said vertical MOS transistor operates as a first electrostatic discharge protection device.   
     
     
         9 . The semiconductor device as defined in  claim 8  further comprising an external terminal that receives/outputs a signal from/to an external source; wherein
 said external terminal and said pad are electrically connected to each other. 
 
     
     
         10 . The semiconductor device as defined in  claim 8 , wherein an upper end of said gate electrode is formed at a position independently of a position of a bottom surface of said upper diffusion layer. 
     
     
         11 . The semiconductor device as defined in  claim 8 , further comprising a fixed potential wiring electrically connected to said upper diffusion layer. 
     
     
         12 . The semiconductor device as defined in  claim 8 , wherein
 said vertical MOS transistor comprises a vertical MOS transistor of a first conductivity type and a vertical MOS transistor of a second conductivity type;   said upper diffusion layer of a vertical MOS transistor of the second conductivity type is electrically connected to a ground potential wiring; and   said upper diffusion layer of said vertical MOS transistor of the first conductivity type is electrically connected to a power supply potential wiring.   
     
     
         13 . The semiconductor device as defined in  claim 12 , wherein
 said vertical MOS transistors of the first and second conductivity types respond to a signal supplied to said gate electrode of each transistor, operate as output transistors, and output via said pad.   
     
     
         14 . The semiconductor device as defined in  claim 8 , further comprising a second electrostatic discharge protection device; wherein
 said vertical MOS transistor is a trigger transistor that serves to start an operation of said second electrostatic discharge protection device.   
     
     
         15 . A semiconductor device, comprising:
 a vertical MOS transistor including a semiconductor substrate having a silicon pillar, a gate electrode formed along a sidewall of said silicon pillar, a gate insulating film formed between said gate electrode and said silicon pillar, an upper diffusion layer formed on the top of said silicon pillar as one of source and drain electrodes, and a lower diffusion layer formed lower than said upper diffusion layer in said semiconductor substrate as the other of said source and drain electrodes; and   a pad electrically connected to said lower diffusion layer; wherein   breakdown occurs between said lower diffusion layer and said semiconductor substrate and a surge voltage is discharged when said surge voltage is applied.   
     
     
         16 . The semiconductor device as defined in  claim 15 , further comprising an external terminal that receives/outputs a signal from/to an external source; wherein
 said external terminal and said pad are electrically connected to each other.   
     
     
         17 . The semiconductor device as defined in  claim 15 , wherein an upper end of said gate electrode is formed at a position independently of a position of a bottom surface of said upper diffusion layer. 
     
     
         18 . The semiconductor device as defined in  claim 15 , further comprising a fixed potential wiring electrically connected to said upper diffusion layer. 
     
     
         19 . The semiconductor device as defined in  claim 15 , wherein
 said vertical MOS transistor comprises a vertical MOS transistor of a first conductivity type and a vertical MOS transistor of a second conductivity type;   said upper diffusion layer of said vertical MOS transistor of the second conductivity type is electrically connected to a ground potential wiring; and   said upper diffusion layer of said vertical MOS transistor of the first conductivity type is electrically connected to a power supply potential wiring.   
     
     
         20 . The semiconductor device as defined in  claim 19 , wherein
 said vertical MOS transistor of the first and second conductivity types respond to a signal supplied to said gate electrode of each transistor, operate as output transistors, and output via said pad.