US2014101407A1PendingUtilityA1

Selectable address translation mechanisms

Assignee: IBMPriority: Oct 8, 2012Filed: Mar 7, 2013Published: Apr 10, 2014
Est. expiryOct 8, 2032(~6.2 yrs left)· nominal 20-yr term from priority
G06F 12/1018G06F 12/1009G06F 12/1027
52
PatentIndex Score
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Claims

Abstract

An address translation capability is provided in which translation structures of different types are used to translate memory addresses from one format to another format. Multiple translation structure formats (e.g., multiple page table formats, such as hash page tables and hierarchical page tables) are concurrently supported in a system configuration, and the use of a particular translation structure format in translating an address is selectable.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A method of facilitating translation of memory addresses, said method comprising:
 obtaining, by a processor, a memory address to be translated, the processor having a first type of address translation structure and a second type of address translation structure available for translating the memory address, wherein the first type is structurally different from the second type; and   selecting, by the processor, one type of address translation structure of the first type of address translation structure and the second type of address translation structure to be used in translating the memory address.   
     
     
         2 . The method of  claim 1 , further comprising:
 obtaining, by the processor, a first address to be translated to a second address; and   using a third type of address translation structure to translate the first address to the second address, the second address being the memory address to be translated by the selected one type of address translation structure.   
     
     
         3 . The method of  claim 2 , wherein the selected one type of address translation structure is different from the third type of address translation structure. 
     
     
         4 . The method of  claim 3 , wherein the third type of address translation structure uses a hierarchical translation structure and the selected one type of address translation structure uses a hash translation structure. 
     
     
         5 . The method of  claim 2 , further comprising selecting the third type of address translation structure from a plurality of types of address translation structures. 
     
     
         6 . The method of  claim 5 , wherein the plurality of types of address translation structures include at least one of a hierarchical address translation structure, a hash translation structure, an offset translation structure, a combination type translation structure, and a segmentation type translation structure. 
     
     
         7 . The method of  claim 5 , wherein the selecting of the third type of address translation structure is independent of the selecting of the one type of address translation structure. 
     
     
         8 . The method of  claim 2 , wherein the first address comprises a guest virtual address, the second address comprises a guest physical address, and wherein the method further comprises translating the guest physical address to a host physical address. 
     
     
         9 . The method of  claim 8 , wherein the host physical address corresponds to an address of a partition executing under control of at least another level of virtualization, and wherein the method further comprises translating the host physical address to another host physical address. 
     
     
         10 . The method of  claim 1 , wherein at least one of the first type of address translation structure and the second type of address translation structure is selected from a set of translation types consisting of a hierarchical translation structure, a hash translation structure, and an offset translation structure.

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