US2014101377A1PendingUtilityA1

Solid state memory (ssm), computer system including an ssm, and method of operating an ssm

Assignee: SAMSUNG ELECTRONICS CO LTDPriority: Aug 14, 2007Filed: Dec 10, 2013Published: Apr 10, 2014
Est. expiryAug 14, 2027(~1 yrs left)· nominal 20-yr term from priority
G06F 3/0688G06F 3/0605G06F 3/0659G11C 16/10G06F 12/08G06F 3/0649G06F 3/0658G06F 2212/7202G06F 3/0679G06F 12/14G11C 11/56G06F 3/0604G06F 3/0647G06F 12/0246G06F 12/00
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Claims

Abstract

In one aspect, data is stored in a solid state memory which includes first and second memory layers. A first assessment is executed to determine whether received data is hot data or cold data. Received data which is assessed as hot data during the first assessment is stored in the first memory layer, and received data which is first assessed as cold data during the first assessment is stored in the second memory layer. Further, a second assessment is executed to determine whether the data stored in the first memory layer is hot data or cold data. Data which is then assessed as cold data during the second assessment is migrated from the first memory layer to the second memory layer.

Claims

exact text as granted — not AI-modified
1 - 26 . (canceled) 
     
     
         27 . A solid state device comprising:
 a first memory;
 a second memory, the first memory being capable of operating at a higher speed than the second memory; and 
   a control unit configured to determine whether an available area of the first memory is less than a predetermined value, the control unit being configured to determine whether data stored in the first memory is a first-type data or a second-type data, the control unit being configured to move the data stored in the first memory to the second memory based on the determination whether the available area of the first memory is less than the predetermined value and on the determination whether the data stored in the first memory is the first-type data or the second-type data.   
     
     
         28 . The solid state device of  claim 27 , wherein, if the data stored in the first memory is determined as the second-type data, the data that is stored in the first memory and is determined as the second data is moved to the second memory. 
     
     
         29 . The solid state device of  claim 27 , wherein, if the available area of the first memory is less than the predetermined value, the data stored in the first memory is moved to the second memory. 
     
     
         30 . The solid state device of  claim 27 , wherein the control unit is configured to determine whether a write count of the data stored in the first memory is equal to or greater than a predetermined count value. 
     
     
         31 . The solid state device of  claim 30 , wherein the data stored in the first memory is determined to be the first-type data if the write count of the data is equal to or greater than the predetermined count value, and the data is determined to be the second-type data if the write count of the data is less than the predetermined count value. 
     
     
         32 . The solid state device of  claim 27 , wherein the control unit is configured to determine whether a size of the data is less than a predetermined size value before the data is initially stored in the first memory or in the second memory. 
     
     
         33 . The solid state device of  claim 32 , the data is initially stored in the first memory if the size of the data is less than the predetermined size value, and the data is initially stored in the second memory if the size of the data is equal to or greater than the predetermined size value. 
     
     
         34 . The solid state device of  claim 33 , wherein the predetermined size value is 32 KB. 
     
     
         35 . The solid state device of  claim 27 , wherein both the first memory and the second memory include multi-level memory cells, the number of bit per cell in the second memory being greater than the number of bit per cell in the first memory. 
     
     
         36 . The solid state device of  claim 27 , wherein the first memory includes single-level memory cells, and the second memory includes multi-level memory cells. 
     
     
         37 . The solid state device of  claim 36 , wherein the first memory is a single-level cell flash memory, and the second memory is a multi-level cell flash memory. 
     
     
         38 . The solid state device of  claim 27 , wherein the control unit determines whether the data stored in the first memory is the first-type data or the second-type data only if the available area of the first memory is less than the predetermined capacity value. 
     
     
         39 . The solid state device of  claim 27 , wherein a storage capacity of the second memory is higher than a storage capacity of the first memory. 
     
     
         40 . A method of storing data to a non-volatile memory device including a first memory and a second memory, the first memory being capable of operating at a higher speed than the second memory, comprising:
 determining by a control unit whether the data stored in the first memory is a first-type data or a second-type data;   determining whether an available area of the first memory is less than a predetermined value; and   moving the data from the first memory to the second memory based the determination whether the available area of the first memory is less than the predetermined value and on the determination whether the data stored in the first memory is the first-type data or the second-type data.   
     
     
         41 . The method of  claim 40 , wherein the moving the data from the first memory to the second memory is performed if the available area of the first memory is less than the predetermined value. 
     
     
         42 . The method of  claim 40 , wherein the moving the data from the first memory to the second memory if the data is determined as the second-type data. 
     
     
         43 . The method of  claim 40  further comprising:
 determining whether a size of the data is less than a predetermined size value before the data is initially stored in the first memory or in the second memory; and 
 initially storing the data in the first memory if the size of the data is less than the predetermined size value, and storing the date in the second memory if the size of the data is equal to or greater than the predetermined size value. 
 
     
     
         44 . A solid state device comprising:
 a first memory;
 a second memory, the first memory being capable of operating at a higher speed than the second memory; and 
   a control unit configured to determine whether a size of received data is less than a predetermined size value, the control unit being configured to determine whether an available area of the first memory is less than a predetermined area value, the control unit being configured to determine whether a write count of data stored in the first memory is equal to or greater than a predetermined count value,   wherein the received data is initially stored in the first memory if the size of the received data is less than the predetermined size value, and the received data is initially stored in the second memory if the size of the received data is equal to or greater than the predetermined size value, and   whether the data stored in the first memory is moved to the second memory if the available area of the first memory is less than the predetermined area value and the write count of data stored in the first memory is equal to or greater than the predetermined count value.   
     
     
         45 . The solid state device of  claim 44 , wherein the control unit determines whether the write count of the data stored in the first memory is equal to or greater than the predetermined count value when the available area of the first memory is less than the predetermined area value. 
     
     
         46 . The solid state device of  claim 44 , wherein the control unit determines whether the write count of the data stored in the first memory is equal to or greater than the predetermined count value, when no read or write request is received.

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