Multi-processor device

Abstract

The present invention intends to provide a high-performance multi-processor device in which independent buses and external bus interfaces are provided for each group of processors of different architectures, if a single chip includes a plurality of multi-processor groups. A multi-processor device of the present invention comprises a plurality of processors including first and second groups of processors of different architectures such as CPUs, SIMD type super-parallel processors, and DSPs, a first bus which is a CPU bus to which the first processor group is coupled, a second bus which is an internal peripheral bus to which the second processor group is coupled, independent of the first bus, a first external bus interface to which the first bus is coupled, and a second external bus interface to which the second bus is coupled, over a single semiconductor chip.

1 - 18 . (canceled) 
     
     
         19 . A semiconductor device comprising:
 a plurality of a first type of processors disposed in a first layout region of a single chip in plan view and being controlled using a first clock, the signal chip having a rectangular shape with four sides in plan view;   a plurality of a second type of processors disposed separately from the plurality of the first type of processors in a second layout region of the single chip in plan view, each said second type of processor having a different architecture from said first type of processors and being controlled using a second clock which differs in frequency or phase from the first clock;   a first bus provided over the single chip to which the plurality of the first type of processors are coupled;   a second bus provided over the single chip to which the plurality of the second type of processors are coupled;   a first external bus interface provided over the single chip, to which a first external bus provided external to the single chip is coupled; and   a second external bus interface provided over the single chip, to which a second external bus provided external to the single chip is coupled,   wherein the plurality of the first type of processors is configured to access the first external bus via the first bus and the first external bus interface,   wherein the plurality of the second type of processors is configured to access the second external bus via the second bus and the second external bus interface, and   wherein, in plan view, the first external bus interface has a portion disposed adjacent to a first side of the four sides of the single chip, and the second external bus interface has a portion disposed adjacent to a second side, different from the first side, of the four sides of the single chip.   
     
     
         20 . The semiconductor device according to  claim 19 ,
 wherein the first and second sides of the single chip are opposite each other.   
     
     
         21 . The semiconductor device according to claim  20 ,
 wherein the second external bus interface has another portion disposed adjacent to a third side different from the first and second sides, of the four sides of the single chip.   
     
     
         22 . The semiconductor device according to  claim 19 ,
 wherein the plurality of the first type of processors is configured to access the second external bus via the first bus, the second bus, and the second external bus interface.   
     
     
         23 . The semiconductor device according to  claim 19 ,
 wherein the plurality of the first type of processors has a symmetric multiple structure and the plurality of the second type of processors has a symmetric multiple structure different from the plurality of the first type of processors in architecture.   
     
     
         24 . The semiconductor device according to  claim 19 ,
 wherein the first type of processor has a first Symmetric Multiple Processor (SMP) structure, and the second type of processor has a second SMP structure which is different from the first SMP structure.   
     
     
         25 . The semiconductor device according to  claim 19 ,
 wherein the plurality of the first type of processors is controlled with a first clock and the plurality of the second type of processors is controlled with a second clock different from the first clock in frequency or phase.