Gate driving circuit and method for driving semiconductor device

Abstract

A gate driving circuit and method can improve the tradeoff relation between the noise and the loss caused in the turn-OFF switching of semiconductor device. The gate driving circuit includes first and second series circuits. The first series circuit includes first and second MOSFETs connected in series. The gate terminal of the semiconductor device is connected to a negative potential side of the first MOSFET and a positive potential side of the second MOSFET. The emitter of the semiconductor device is connected to the negative potential side of the second MOSFET or a DC power source. The second series circuit includes a capacitor and a third MOSFET connected in series. The second series circuit is connected in parallel with the second MOSFET. The semiconductor device is turned OFF by turning ON the second and third MOSFETs and turning OFF the first MOSFET.

What is claimed is: 
     
         1 . A method of controllably turning ON and OFF a semiconductor device having a gate, a collector, and an emitter, the method comprising the steps of:
 feeding at least a positive voltage to the gate of the semiconductor device for controllably turning ON and OFF the semiconductor device;   setting a changing rate of a voltage between the collector and the emitter of the semiconductor device to be large until the voltage between the collector and the emitter of the semiconductor device reaches a DC voltage applied between the collector and the emitter of the semiconductor device to turn OFF the semiconductor device; and   setting the changing rate of the voltage between the collector and the emitter of the semiconductor device to be small after the voltage between the collector and the emitter of the semiconductor device reaches the DC voltage applied between the collector and the emitter of the semiconductor device.   
     
     
         2 . The method according to  claim 1 , further comprising the steps of:
 providing a first series circuit having a first MOSFET and a second MOSFET connected in series with the first MOSFET;   providing a second series circuit having a capacitor and a third MOSFET connected in series with the capacitor;   connecting a fourth MOSFET in parallel with the second MOSFET;   connecting the first series circuit to a positive side and a negative side of a DC power supply;   connecting the second series circuit in parallel with the second MOSFET;   connecting the gate of the semiconductor device to a negative potential side of the first MOSFET and a positive potential side of each of the second, third, and fourth MOSFETs, and the emitter of the semiconductor device to a negative potential side of each of the second, third, and fourth MOSFETs;   concurrently inputting a common ON/OFF activating signal to both the second and third MOSFETs to turn ON/OFF both the second and third MOSFETs;   turning OFF the first MOSFET and turning ON the second and third MOSFETs to turn OFF the semiconductor device;   turning ON the fourth MOSFET as the semiconductor device is brought into an OFF state to keep the semiconductor device in the OFF state; and   always turning ON the third MOSFET, from an OFF-state, before turning ON the second MOSFET to draw charges accumulated between the gate and the emitter of the semiconductor device into the capacitor, by having at least one of the gate resistance or the ON-state resistance of the second MOSFET set higher than the corresponding gate resistance or the ON-state resistance of the third MOSFET, each time the semiconductor device is switched OFF,   wherein the second series circuit prevents turn-OFF noise and turn-OFF loss of the semiconductor device.   
     
     
         3 . The method according to  claim 2 , wherein the ON-state resistance of the second MOSFET is higher than the ON-state resistance of the third MOSFET to turn on the third MOSFET before turning ON the second MOSFET. 
     
     
         4 . The method according to  claim 3 , wherein the channel length in the second MOSFET is set longer than the channel length in the third MOSFET to set the ON-state resistance of the second MOSFET higher than the ON-state resistance of the third MOSFET. 
     
     
         5 . The method according to  claim 2 , wherein the second series circuit increases a change rate dv/dt of a voltage Vce when Vce<Vdc, Vdc being a DC voltage, while the change rate dv/dt of the voltage Vce remains substantially the same when Vce>Vdc, relative to when the gate driving circuit is omitted from the second series circuit.