Vertical transistor with hardening implantation

Abstract

A vertical transistor includes a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. Each pillar structure forms a vertical pillar transistor having a top surface and a side surface orthogonal to the top surface. Then a hardening ion species is implanted into the vertical pillar transistor top surface. Then the vertical pillar transistor side surface is oxidized to form a side surface oxide layer. The side surface oxide layer is removed to form vertical pillar transistor having rounded side surfaces.

What is claimed is: 
     
         1 . An apparatus comprising:
 a vertical pillar transistor extending orthogonally from a semiconductor wafer, the vertical pillar transistor comprising a planar top surface and a rounded side surface, the rounded side surface is orthogonal to the planar top surface, wherein the top surface includes a hardening ion implant species;   an electrically conductive gate material layer on the rounded side surfaces; and   a memory cell in electrical connection with the vertical pillar transistor.   
     
     
         2 . The apparatus according to  claim 1  wherein the memory cell is an RRAM or STRAM memory cell. 
     
     
         3 . The apparatus according to  claim 1  wherein the memory cell is electrically between the vertical pillar transistor and the semiconductor wafer. 
     
     
         4 . The apparatus according to  claim 1  wherein the vertical pillar transistor is electrically between the memory cell and the semiconductor wafer. 
     
     
         5 . The apparatus according to  claim 1  further comprising a gate oxide layer between the rounded side surfaces and the electrically conductive gate material layer. 
     
     
         6 . The apparatus according to  claim 1  wherein the hardening ion implant species comprise nitrogen. 
     
     
         7 . The apparatus according to  claim 1  wherein the hardening ion implant species is not in the rounded side surface. 
     
     
         8 . The apparatus according to  claim 1  wherein the planar top surface comprises a silicon oxynitride oxide layer and the rounded side surface does not comprise a silicon oxynitride oxide layer. 
     
     
         9 . The apparatus according to  claim 8  further comprising a gate oxide layer between the rounded side surfaces and the electrically conductive gate material layer. 
     
     
         10 . The apparatus according to  claim 1  further comprising a plurality of vertical pillar transistor extending orthogonally from a semiconductor wafer, wherein at least selected vertical pillar transistors comprise a planar top surface and rounded side surfaces, the rounded side surfaces are orthogonal to the planar top surface, wherein the top surface includes a hardening ion implant species, and an electrically conductive gate material layer is on the rounded side surfaces, and a plurality of memory cells forming a memory array, where each memory cell is in electrical connection with a selected vertical pillar transistor. 
     
     
         11 . An apparatus comprising:
 a vertical pillar transistor extending orthogonally from a semiconductor wafer, the vertical pillar transistor comprising a planar top surface and a rounded side surface, the rounded side surface and the planar top surface meet at a vertex and form an angle, wherein the top surface includes a hardening ion implant species and the rounded side surface does not include the hardening ion implant species;   an electrically conductive gate material layer on the rounded side surfaces; and   a memory cell in electrical connection with the vertical pillar transistor.   
     
     
         12 . The apparatus according to  claim 11  wherein the hardening ion species is nitrogen. 
     
     
         13 . The apparatus according to  claim 11  wherein the top surface is a parallel with the major surface of the semiconductor wafer. 
     
     
         14 . The apparatus according to  claim 11  wherein the angle is a right angle. 
     
     
         15 . The apparatus according to  claim 11  wherein the memory cell is an RRAM or STRAM memory cell. 
     
     
         16 . The apparatus according to  claim 11  wherein the memory cell is electrically between the vertical pillar transistor and the semiconductor wafer. 
     
     
         17 . The apparatus according to  claim 11  wherein the vertical pillar transistor is electrically between the memory cell and the semiconductor wafer. 
     
     
         18 . The apparatus according to  claim 11  further comprising a gate oxide layer between the rounded side surfaces and the electrically conductive gate material layer. 
     
     
         19 . The apparatus according to  claim 11  wherein the hardening ion implant species comprise nitrogen. 
     
     
         20 . The apparatus according to  claim 11  wherein the planar top surface comprises a silicon oxynitride oxide layer and the rounded side surface does not comprise a silicon oxynitride oxide layer.