Semiconductor device

Abstract

A method for fabricating a semiconductor device is described. A stacked gate dielectric is formed over a substrate, including a first dielectric layer, a second dielectric layer and a third dielectric layer from bottom to top. A conductive layer is formed on the stacked gate dielectric and then patterned to form a gate conductor. The exposed portion of the third and the second dielectric layers are removed with a selective wet cleaning step. S/D extension regions are formed in the substrate with the gate conductor as a mask. A first spacer is formed on the sidewall of the gate conductor and a portion of the first dielectric layer exposed by the first spacer is removed. S/D regions are formed in the substrate at both sides of the first spacer. A metal silicide layer is formed on the S/D regions.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a gate conductor on a substrate;   a stacked gate dielectric between the gate conductor and the substrate, comprising, from bottom to top, a first dielectric layer, a second dielectric layer and a third dielectric layer, wherein a sidewall of the second dielectric layer is aligned with a sidewall of the gate conductor;   a first spacer on the sidewall of the gate conductor;   source/drain (S/D) extension regions in the substrate outside of the sidewall of the gate conductor;   S/D regions in the substrate outside of a sidewall of the first spacer; and   a metal silicide layer at least on the S/D regions.   
     
     
         2 . The semiconductor device of  claim 1 , further comprising a second spacer between the gate conductor and first spacer, wherein a sidewall of the first dielectric layer is aligned with a sidewall of the second spacer. 
     
     
         3 . The semiconductor device of  claim 1 , wherein a sidewall of the first dielectric layer is aligned with the sidewall of the first spacer. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the second dielectric layer comprises a charge-trapping layer. 
     
     
         5 . The semiconductor device of  claim 4 , wherein the charge-trapping layer comprises silicon nitride. 
     
     
         6 . The semiconductor device of  claim 5 , which comprises a memory cell, wherein the gate conductor comprises dopes polysilicon, the first and the third dielectric layers comprise silicon oxide, and the substrate, the first dielectric layer, the second dielectric layer, the third dielectric layer and the gate conductor constitute a semiconductor-oxide-nitride-oxide-silicon (SONOS) structure of the memory cell. 
     
     
         7 . The semiconductor device of  claim 1 , wherein the gate conductor comprises doped polysilicon, and the metal silicide layer is also on the gate conductor.