Semiconductor devices including multilayer source/drain stressors and methods of manufacturing the same

Abstract

A semiconductor device including source drain stressors and methods of manufacturing the same are provided. The methods may include forming a recess region in the substrate at a side of a gate pattern, and an inner surface of the recess region may include a first surface of a (100) crystal plane and a second surface of one of {111} crystal planes. The method may further include performing a first selective epitaxial growth (SEG) process to form a base epitaxial pattern on the inner surface of the recess region at a process pressure in a range of about 50 Torr to about 300 Torr. The method may also include performing a second selective epitaxial growth (SEG) process to form a bulk epitaxial pattern on the base epitaxial pattern.

1 .- 9 . (canceled) 
     
     
         10 . A method of manufacturing a semiconductor device comprising:
 forming a gate pattern on a substrate comprising a first semiconductor element;   forming a recess region in the substrate at a side of the gate pattern, an inner surface of the recess region including a first surface of a (100) crystal plane and a second surface of one of {111} crystal planes;   performing a first selective epitaxial growth (SEG) process to form a base epitaxial pattern on the inner surface of the recess region at a process pressure in a range of about 50 Torr to about 300 Torr, the base epitaxial pattern comprising a second semiconductor element different from the first semiconductor element; and   performing a second selective epitaxial growth (SEG) process to form a bulk epitaxial pattern comprising the second semiconductor element on the base epitaxial pattern.   
     
     
         11 . The method of  claim 10 , wherein a second semiconductor element concentration in the base epitaxial pattern is less than a second semiconductor element concentration in the bulk epitaxial pattern, and wherein the base epitaxial pattern has a first thickness on the first surface and a second thickness on the second surface, and a ratio of the second thickness to the first thickness of the base epitaxial pattern is in a range about ¾ to about 1. 
     
     
         12 . The method of  claim 10 , wherein the substrate comprises first dopants of a first conductivity type and the bulk epitaxial pattern comprises second dopants of a second conductivity type different from the first conductivity type, and wherein the base epitaxial pattern is free of the second dopants or a second dopant concentration in the base epitaxial pattern is less than a second dopant concentration in the bulk epitaxial pattern. 
     
     
         13 . The method of  claim 10 , wherein forming the recess region comprises:
 performing an anisotropic dry etching process to form a concave region in the substrate at a side of the gate pattern; and   performing an anisotropic wet etching process in the concave region to form the recess region,   wherein the anisotropic wet etching process uses {111} crystal planes of the substrate as etch stop surfaces.   
     
     
         14 . The method of  claim 10 , further comprising:
 performing an additional selective epitaxial growth (SEG) process to form a buffer epitaxial pattern comprising the second semiconductor element on the base epitaxial pattern before performing the second SEG process,   wherein a process pressure of the additional SEG process is lower than the process pressure of the first SEG process.   
     
     
         15 . The method of  claim 14 , wherein a second semiconductor element concentration in the buffer epitaxial pattern is less than a second semiconductor element concentration in the bulk epitaxial pattern and is greater than a second semiconductor element concentration in the base epitaxial pattern. 
     
     
         16 . A method of manufacturing an integrated circuit device comprising:
 forming a recess in a substrate comprising a first element, wherein an inner surface of the recess comprises a first surface of a (100) crystal plane and a second surface of one of {111} crystal planes;   forming a first epitaxial layer on the inner surface of the recess; and   forming a second epitaxial layer in the recess on the first epitaxial layer, wherein the first epitaxial layer extends between the inner surface of the recess and the second epitaxial layer, and wherein the second epitaxial layer comprises a second element having a lattice size different from a lattice size of the first element.   
     
     
         17 . The method of  claim 16 , wherein forming the first epitaxial layer comprises performing an epitaxial growth process at a process pressure in a range of about 50 Torr to about 300 Torr. 
     
     
         18 . The method of  claim 16 , wherein the first epitaxial layer comprises a portion of a first thickness on the first surface and a portion of a second thickness on the second surface, and wherein a ratio of the second thickness to the first thickness is in a range of about ¾ to about 1. 
     
     
         19 . The method of  claim 16 , further comprising forming a gate structure on the substrate, wherein a portion of the recess, whose inner surface comprises the second surface, is tapered toward a region under the gate structure. 
     
     
         20 . The method of  claim 16 , wherein the first epitaxial layer comprises the second element, and wherein a second element concentration of the first epitaxial layer is less than a second element concentration of the second epitaxial layer. 
     
     
         21 . The method of  claim 16 , wherein the second epitaxial layer comprises a first dopant of a first conductivity type, and wherein a first dopant concentration of the second epitaxial layer is greater than a first dopant concentration of the first epitaxial layer. 
     
     
         22 . The method of  claim 21 , wherein the first epitaxial layer is free of the first dopant. 
     
     
         23 . The method of  claim 21 , wherein the substrate comprise a second dopant of a second conductivity type opposite to the first conductivity type. 
     
     
         24 . The method of  claim 16 , further comprising forming a third epitaxial layer on the first epitaxial layer before forming the second epitaxial layer. 
     
     
         25 . The method of  claim 24 , wherein forming the first epitaxial layer comprises performing a first epitaxial growth process at a first process pressure and forming the third epitaxial layer comprises performing a second epitaxial growth process at a second process pressure less than the first process pressure. 
     
     
         26 . The method of  claim 24 , wherein the first epitaxial layer comprises a portion of a first thickness on the first surface and a portion of a second thickness on the second surface, and the third epitaxial layer comprises a portion of a third thickness on the first surface and a portion of a fourth thickness on the second surface, and wherein a ratio of the second thickness to the first thickness is greater than a ratio of the fourth thickness to the third thickness. 
     
     
         27 . The method of  claim 24 , wherein the first and third epitaxial layers comprise the second element, and wherein a second element concentration of the third epitaxial layer is greater than a second element concentration of the first epitaxial layer and is less than a second element concentration of the second epitaxial layer. 
     
     
         28 . The method of  claim 24 , wherein the second and third epitaxial layers comprise a dopant of a first conductivity type, and wherein a dopant concentration of the second epitaxial layer is greater than a dopant concentration of the third epitaxial layer. 
     
     
         29 . The method of  claim 28 , wherein the first epitaxial layer is free of the dopant or a dopant concentration of the first epitaxial layer is less than the dopant concentration of the third epitaxial layer.