Metal-insulator-metal (mim) capacitor

Abstract

There is disclosed a metal-insulator-metal, MIM, capacitor. The MIM capacitor comprises a MIM stack formed within an interconnect metal layer. The interconnect metal layer is utilised as an electrical connection to a metal layer of the MIM stack.

1 . A metal-insulator-metal, MIM, capacitor, comprising:
 a MIM stack formed within an interconnect metal layer, wherein the interconnect metal layer is adapted to provide an electrical connection to a metal layer of the MIM stack.   
     
     
         2 . The MIM capacitor of  claim 1 , wherein the interconnect metal layer is an Nth metal layer for a BiCMOS process having an N+1th interconnect metal layer. 
     
     
         3 . The MIM capacitor of  claim 1 , further comprising:
 a first metal layer formed on a substrate, wherein the MIM stack is formed on the first metal layer;   an opening formed in the substrate that exposes at least one portion of the first metal layer below a region of the MIM stack; and   a via metal layer formed in the opening of the substrate so as to form a via connecting to the first metal layer,   wherein the at least part of interconnect metal layer is formed on the MIM stack.   
     
     
         4 . The MIM capacitor of  claim 1  further comprising an anti-reflective coating layer formed on the interconnect metal layer, wherein the anti-reflective coating layer comprises titanium or titanium alloy. 
     
     
         5 . The MIM capacitor of  claim 1 , wherein the interconnect metal layer comprises aluminum, aluminum alloy, copper, or copper alloy. 
     
     
         6 . The MIM capacitor of  claim 1 , wherein at least one of the metal layers of the MIM stack comprises titanium or titanium alloy, and wherein the insulator layer of the MIM stack comprises a metal oxide or silicon nitride. 
     
     
         7 . A method manufacturing a metal-insulator-metal, MIM, capacitor, comprising:
 forming a MIM stack within an interconnect metal layer, wherein the interconnect metal layer forms an electrical connection to a metal layer of the MIM stack.   
     
     
         8 . The method of  claim 7 , wherein the interconnect metal layer is an Nth metal layer for a BiCMOS process having an N+1th interconnect metal layer. 
     
     
         9 . The method of  claim 7 , further comprising:
 forming an opening in a substrate;   forming a via metal layer in the opening of the substrate so as to form a via in the substrate;   forming a first metal layer on the substrate;   forming the MIM stack on the first metal layer; and   forming at least part of the interconnect metal layer on the MIM stack.   
     
     
         10 . The method of  claim 7 , further comprising forming an anti-reflective coating layer on the interconnect metal layer, wherein the anti-reflective coating layer comprises titanium or titanium alloy. 
     
     
         11 . The method of  claim 7 , wherein the interconnect metal layer comprises aluminum, aluminum alloy, copper, or copper alloy. 
     
     
         12 . The method of  claim 7 , wherein at least one of the metal layers of the MIM stack comprises titanium or titanium alloy, and wherein the insulator layer of the MIM stack comprises a metal oxide or silicon nitride. 
     
     
         13 . The method of  claim 7 , further comprising:
 forming a mask layer on the interconnect metal layer;   patterning the mask layer to expose at least one region of the interconnect layer and to retain at least one portion of the mask layer above the MIM stack; and   etching the exposed at least one region through the interconnect metal layer and the first metal layer to form at least one trench in the substrate.   
     
     
         14 . The method of  claim 13 , wherein a horizontal dimension of the at least a portion of the mask layer above the MIM stack is less than the corresponding horizontal dimension of the MIM stack, such that the step of etching comprises etching through the MIM stack. 
     
     
         15 . A BiCMOS integrated circuit comprising a MIM capacitor according to  claim 1 .