Semiconductor devices with silicon-germanium channels including hydrogen

Abstract

A semiconductor device is fabricated by providing a substrate including a silicon channel layer and a silicon-germanium channel layer, forming gate structures disposed on the silicon channel layer and on the silicon-germanium channel layer, forming a first protection layer to cover the resultant structure including the gate structures, and injecting hydrogen and/or its isotopes into the silicon-germanium channel layer. The silicon and silicon-germanium channel layers may be oriented along a <100> direction. Related devices are also described.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 an NMOS transistor including a channel layer and a gate structure on the channel layer; and   a PMOS transistor including a channel layer and a gate structure on the channel layer,   wherein the channel layer of the NMOS transistor comprises silicon, and the channel layer of the PMOS transistor comprises silicon-germanium and includes therein hydrogen and/or an isotope thereof.   
     
     
         2 . The device of  claim 1 , further comprising a first protection layer on the NMOS and PMOS transistors including the gate structures, wherein the first protection layer comprises a tensile material. 
     
     
         3 . The device of  claim 2 , further comprising a second protection layer on the first protection layer, wherein the second protection layer comprises a material having a higher content of hydrogen and/or an isotope thereof than the first protection layer. 
     
     
         4 . The device of  claim 3 , wherein the second protection layer comprises a tensile material. 
     
     
         5 . The device of  claim 2 , further comprising a second protection layer on the first protection layer, wherein the second protection layer comprises a material having a greater process-induced charging property than the first protection layer. 
     
     
         6 . The device of  claim 2 , further comprising gate spacers disposed on sidewalls of the gate structures of the NMOS and PMOS transistors, respectively, to spatially separate the first protection layer from the sidewalls of the gate structures. 
     
     
         7 . A semiconductor device, comprising:
 a PMOS transistor including a channel layer and a gate structure on the channel layer,   wherein the channel layer of the PMOS transistor comprises silicon-germanium and includes therein hydrogen and/or an isotope thereof.   
     
     
         8 . The device of  claim 7 , further comprising a first protection layer on the PMOS transistor including the gate structure, wherein the first protection layer comprises a tensile material. 
     
     
         9 . The device of  claim 8 , further comprising a second protection layer on the first protection layer, wherein the second protection layer comprises a material having a higher content of hydrogen and/or an isotope thereof than the first protection layer. 
     
     
         10 . The device of  claim 8 , further comprising a second protection layer on the first protection layer, wherein the second protection layer comprises a material having a greater process-induced charging property than the first protection layer. 
     
     
         11 . The device of  claim 7 , further comprising gate spacers disposed on a sidewall of the gate structure of the PMOS transistor, to spatially separate the first protection layer from the sidewall of the gate structure.