Semiconductor Device with Increased Breakdown Voltage

Abstract

Optimization of the implantation structure of a metal oxide silicon field effect transistor (MOSFET) device fabricated using conventional complementary metal oxide silicon (CMOS) logic foundry technology to increase the breakdown voltage. The techniques used to optimize the implantation structure involve lightly implanting the gate region, displacing the drain region from the gate region, and implanting P-well and N-well regions adjacent to one another without an isolation region in between.

What is claimed is: 
     
         1 . A semiconductor device formed onto a substrate, comprising:
 a gate region;   a first well region having a first carrier concentration;   a second well region having a second carrier concentration, the first and the second well regions being in substantial contact with each other through a transition region, the transition region being located beneath the gate region;   a drain region having a third carrier concentration, the third carrier concentration being greater than the first carrier concentration; and   a source region having a fourth carrier concentration, the fourth carrier concentration being greater than the second carrier concentration,   wherein the gate region is displaced from the drain region by a portion of the first well region.   
     
     
         2 . The semiconductor device of  claim 1 , further comprising:
 a dielectric region within the portion of the first well region.   
     
     
         3 . The semiconductor device of  claim 2 , wherein the dielectric region comprises:
 a first side and a second side,   wherein the first side is in substantial contact with the drain region, and   wherein the second side is located below a spacer, the spacer being in substantial contact with the gate region.   
     
     
         4 . The semiconductor device of  claim 1 , further comprising:
 a shallow trench isolation region (STI) region within the portion of the first well region.   
     
     
         5 . The semiconductor device of  claim 4 , wherein the STI region comprises:
 a first side and a second side,   wherein the first side is in substantial contact with the drain region, and   wherein the second side is located below a spacer, the spacer being in substantial contact with the gate region.   
     
     
         6 . The semiconductor device of  claim 1 , further comprising:
 a silicide region in substantial contact with a top surface of the drain region.   
     
     
         7 . The semiconductor device of  claim 6 , wherein the silicide region is displaced from the gate region by a portion of a top surface of the substrate that corresponds to the portion of the first well region. 
     
     
         8 . The semiconductor device of  claim 1 , further comprising:
 a channel located within the source region.   
     
     
         9 . The semiconductor device of  claim 1 , wherein the drain region is within the first we  1  region. 
     
     
         10 . The semiconductor device of  claim 1 , wherein the source region is within the second well region. 
     
     
         11 . The semiconductor device of  claim 1 , wherein the first well region and the drain region comprise a first type of material. 
     
     
         12 . The semiconductor device of  claim 1 , wherein the second well region comprises:
 a first type of material, and wherein
 the source region comprises a second type of material, the first type of material being different from the second type of material. 
   
     
     
         13 . A semiconductor device, comprising:
 a source region within a substrate;   a drain region within the substrate;   a gate region substantially overlapping at least a portion of the source region; and   a dielectric region configured to:
 prevent overlap between the gate region and the drain region; and 
 provide resistance in a current path between the source region and the drain region. 
   
     
     
         14 . The semiconductor device of  claim 13 , wherein the dielectric region is in contact with the drain region. 
     
     
         15 . The semiconductor device of  claim 13 , wherein the dielectric region substantially overlaps at least a portion of a spacer, the spacer being in substantial contact with the gate region. 
     
     
         16 . The semiconductor device of  claim 13 , wherein the dielectric region is a shallow trench isolation (STI) region. 
     
     
         17 . The semiconductor device of  claim 13 , further comprising:
 a first well region within the substrate;   a second well within the substrate, the first and the second wells regions being in substantial contact with each other through a transition region, the transition region being positioned below the gate region.   
     
     
         18 . The semiconductor device of  claim 13 , wherein the drain region and first well region comprises:
 a first type of material.   
     
     
         19 . The semiconductor device of  claim 13 , wherein the source region comprises:
 a first type of material, and   wherein the second well region comprises:
 a second type of material, the first type of material being different from the second type of material. 
   
     
     
         20 . The semiconductor device of  claim 13 , further comprising:
 a silicide region in substantial contact with the drain region and displaced from the gate region by the dielectric region and a spacer.