Leakage reduction in DRAM MIM capacitors

Abstract

A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high-k phase of a subsequently deposited dielectric layer. The high-k dielectric layer includes a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.

1 . A semiconductor layer stack comprising:
 a first layer formed on a substrate,
 wherein the first layer is operable as an electrode; 
   a second layer formed on the first layer,
 wherein the second layer comprises a dielectric material, and 
 wherein the second layer further comprising a dopant; 
   a third layer formed on the second layer,
 wherein the third layer is operable as a blocking layer, 
 wherein the third layer comprises a ternary metal oxide, and 
 wherein a k value of the third layer is between 20 and 50 and a band gap of the third layer is greater than 4.8 eV; and 
   a fourth layer formed on the third layer,
 wherein the fourth layer is operable as an electrode. 
   
     
     
         2 . The semiconductor layer stack of  claim 1  wherein the first layer is one of a metal, metal alloy, conductive metal oxide, conductive metal silicide, conductive metal carbides, conductive metal nitride, or combinations thereof. 
     
     
         3 . The semiconductor layer stack of  claim 2  wherein the first layer is a conductive metal oxide comprising one of molybdenum oxide, tungsten oxide, ruthenium oxide, iron oxide, iridium oxide, chromium oxide, manganese oxide, tin oxide, cobalt oxide, or nickel oxide. 
     
     
         4 . The semiconductor layer stack of  claim 3  wherein the conductive metal oxide is molybdenum oxide. 
     
     
         5 . The semiconductor layer stack of  claim 1  wherein the dielectric material comprises one of aluminum oxide, barium-strontium-titanate (BST), hafnium oxide, hafnium silicate, niobium oxide, lead-zirconium-titanate (PZT), a bilayer of silicon oxide and silicon nitride, silicon oxy-nitride, strontium-titanate (STO), tantalum oxide, titanium oxide, zirconium oxide, or doped versions of the same. 
     
     
         6 . The semiconductor layer stack of  claim 5  wherein the dielectric materials comprises a dopant and wherein the dopant comprises one of Al, Ce, Co, Er, Ga, Gd, Ge, Hf, In, La, Lu, Mg, Mn, Nd, Pr, Sc, Si, Sn, Sr, Y, Zr, or combinations thereof. 
     
     
         7 . The semiconductor layer stack of  claim 1  wherein the third layer comprises one of LaAlO3, GdScO3, SrZrO4, LaLuO3, DyScO3, HfLaOx, ZrLaOx, TiLaOx or combinations thereof. 
     
     
         8 . The semiconductor layer stack of  claim 1  wherein a thickness of the third layer is thinner than a thickness of the second layer. 
     
     
         9 . The semiconductor layer stack of  claim 1  wherein a thickness of the third layer is less than 2.0 nm. 
     
     
         10 . The semiconductor layer stack of  claim 1  wherein a thickness of the third layer is between 0.7 nm and 1.5 nm. 
     
     
         11 . The semiconductor layer stack of  claim 1  wherein a thickness of the third layer is less or equal to 25% of a combined thickness of the second layer, and the third layer. 
     
     
         12 . The semiconductor layer stack of  claim 1  wherein the fourth layer comprises one of cobalt, cobalt nitride, iridium, molybdenum nitride, molybdenum oxide, nickel, nickel nitride, nickel oxide, platinum, palladium, ruthenium, ruthenium oxide, tantalum nitride, titanium nitride, tungsten nitride, vanadium nitride, or combinations thereof. 
     
     
         13 . The semiconductor layer stack of  claim 1  wherein the first layer is subjected to an annealing treatment before the formation of the second layer. 
     
     
         14 . The semiconductor layer stack of  claim 1  wherein the first layer, the second layer, and the third layer are subjected to an annealing treatment after forming the third layer and before forming the fourth layer. 
     
     
         15 . The semiconductor layer stack of  claim 1  wherein the first layer, the second layer, the third layer, and the fourth layer are subjected to an annealing treatment after the formation of the fourth layer. 
     
     
         16 . A semiconductor layer stack comprising:
 a first layer formed on a substrate,
 wherein the first layer is operable as an electrode, and 
 wherein the first layer comprises molybdenum oxide; 
   a second layer formed on the first layer,
 wherein the second layer comprises dielectric material, 
 wherein the second layer comprises a dopant, and 
 wherein the second layer is more than 30% crystalline after a subsequent annealing treatment; 
   a third layer formed on the second layer,
 wherein the third layer is operable as a blocking layer, 
 wherein the third layer comprises LaAlO 3 , and 
 wherein the third layer is amorphous after a subsequent annealing treatment; and 
   a fourth layer formed on the third layer,
 wherein the fourth layer is operable as an electrode. 
   
     
     
         17 . The semiconductor layer stack of  claim 16  further wherein the first layer is subjected to an annealing treatment before the forming of the second layer. 
     
     
         18 . The semiconductor layer stack of  claim 16  further wherein the first layer, the second layer, and the third layer are subjected to an annealing treatment after the forming of the third layer and before the forming of the fourth layer. 
     
     
         19 . The semiconductor layer stack of  claim 16  wherein the first layer, second layer, third layer and fourth layer are subjected to an annealing treatment after the forming of the fourth layer. 
     
     
         20 . The semiconductor layer stack of  claim 16  wherein the fourth layer comprises one of cobalt, cobalt nitride, iridium, molybdenum nitride, molybdenum oxide, nickel, nickel nitride, nickel oxide, platinum, palladium, ruthenium, ruthenium oxide, tantalum nitride, titanium nitride, tungsten nitride, vanadium nitride, or combinations thereof.