Fabrication method of packaging substrate having embedded capacitors
Abstract
A packaging substrate includes: a substrate having a core layer, a cavity penetrating the core layer and circuit layers formed on surfaces of the core layer; a first capacitor disposed in the cavity; a bonding layer formed on the first capacitor in the cavity of the substrate; a second capacitor disposed on the bonding layer so as to be received in the cavity; and a dielectric layer formed on the substrate and in the cavity for covering the first and second capacitors. By stacking the first and second capacitors in the cavity through the bonding layer, the single core layer is embedded with two layers of the capacitors to thereby meet the multi-function requirement.
Claims
exact text as granted — not AI-modified1 - 9 . (canceled)
10 . A fabrication method of a packaging substrate having embedded capacitors, comprising the steps of:
providing a substrate having a core layer, at least a cavity penetrating the core layer and circuit layers formed on surfaces of the core layer; disposing a first capacitor in the at least a cavity of the substrate; forming a bonding layer on the first capacitor; disposing a second capacitor on the bonding layer so as for the at least a cavity of the substrate to receive the first and second capacitors; and forming a dielectric layer on the substrate and in the at least a cavity for covering the first and second capacitors.
11 . The method of claim 10 , wherein the core layer has a plurality of conductive through holes for electrically connecting the circuit layers.
12 . The method of claim 10 , wherein the core layer has opposite first and second surfaces so as for the cavity to be in communication therewith.
13 . The method of claim 12 , wherein the dielectric layer is pressed to be combined with the first and second surfaces of the core layer.
14 . The method of claim 10 , wherein the bonding layer is made of a dielectric material or an insulating material.
15 . The method of claim 10 , wherein the dielectric layer is further formed between the first capacitor and the cavity and also between the second capacitor and the cavity for securing the first and second capacitors in position.
16 . The method of claim 10 , before forming the dielectric layer, further comprising forming an adhesive layer between the first capacitor and the cavity and also between the second capacitor and the cavity for securing the first and second capacitors in position.
17 . The method of claim 10 , further comprising forming on the dielectric layer a built-up structure electrically connecting the first and second capacitors.
18 . The method of claim 17 , further comprising forming an insulating protection layer on the built-up structure and forming a plurality of openings in the insulating protection layer for exposing portions of the built-up structure.
19 . The method of claim 10 , wherein forming the dielectric layer comprises:
attaching a carrier to the first capacitor at one end of the cavity; forming a first dielectric material on the second capacitor at the other end of the cavity; removing the carrier; and forming a second dielectric material on the substrate and the first capacitor and in the cavity so as to form the dielectric layer through a combination of the first and second dielectric materials.Join the waitlist — get patent alerts
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