Method of fabricating a semiconductor package

Abstract

A method of fabricating a semiconductor package is provided, including: providing a substrate having opposite first and second surfaces and a plurality of conductive through holes penetrating the first and second surfaces, disposing the substrate on a first carrier through the second surface thereof, and keeping the first carrier flat and free of warpage; attaching at least a first semiconductor chip to the first surface of the substrate and electrically connecting the first semiconductor chip and the substrate; removing the first carrier; and attaching the substrate to a packaging substrate through the second surface thereof and electrically connecting the substrate and the packaging substrate, thereby preventing the semiconductor package from warpage, increasing product yield, reducing fabrication cost, and improving thermal dissipation.

What is claimed is: 
     
         1 . A method of fabricating a semiconductor package, comprising:
 providing a substrate having opposite first and second surfaces and a plurality of conductive through holes penetrating the first and second surfaces, disposing the substrate on a first carrier through the second surface thereof, and keeping the first carrier flat and free of warpage;   attaching at least a first semiconductor chip to the first surface of the substrate and electrically connecting the first semiconductor chip and the substrate;   removing the first carrier; and   attaching the substrate to a packaging substrate through the second surface thereof and electrically connecting the substrate and the packaging substrate.   
     
     
         2 . The method of  claim 1 , wherein the first semiconductor chip is attached to the first surface of the substrate in a manner that a plurality of conductive bumps are formed between the first surface of the substrate and the first semiconductor chip for electrically connecting the first semiconductor chip and the substrate. 
     
     
         3 . The method of  claim 1 , further comprising forming an underfill between the first semiconductor chip and the first surface of the substrate. 
     
     
         4 . The method of  claim 1 , wherein the substrate is attached to the packaging substrate in a manner that a plurality of conductive bumps are formed between the packaging substrate and the second surface of the substrate for electrical connecting the packaging substrate and the substrate. 
     
     
         5 . The method of  claim 1 , further comprising forming an underfill between the second surface of the substrate and the packaging substrate. 
     
     
         6 . The method of  claim 1 , after removing the first carrier, further comprising disposing the first semiconductor chip on a second carrier opposite to the first surface of the substrate, performing a testing process, and then removing the second carrier. 
     
     
         7 . The method of  claim 6 , further comprising forming a UV release adhesive on the second carrier before disposing the first semiconductor chip on the second carrier, wherein the step of removing the second carrier further comprises removing the UV release adhesive simultaneously, and the second carrier is a UV release tape. 
     
     
         8 . The method of  claim 1 , wherein the first carrier is disposed on a carriage by air suction or electrostatic force to be kept flat and free of warpage. 
     
     
         9 . The method of  claim 1 , further comprising electrically connecting at least a second semiconductor chip to the first semiconductor chip. 
     
     
         10 . The method of  claim 1 , wherein the first carrier is a UV release tape. 
     
     
         11 . The method of  claim 1 , wherein the substrate is a through silicon interposer, and the conductive through holes are made of silicon. 
     
     
         12 . The method of  claim 1 , wherein the substrate further has a redistribution layer formed on the first surface or the second surface thereof and electrically connected to the conductive through holes. 
     
     
         13 . The method of  claim 12 , wherein a dielectric material the redistribution layer is different from that of the substrate. 
     
     
         14 . The method of  claim 1 , wherein the substrate is a through glass interposer and the conductive through holes are made of glass.