Voltage down converter for high speed memory

Abstract

A voltage down converter (VDC) applicable to high-speed memory devices. The VDC includes a steady driver and active driver along with at least one additional transistor. The steady driver and active driver are coupled by a transistor switch during device start-up to provide fast ramp-up to operating voltage and current. After start-up, the steady driver and active drive function to maintain a steady operating voltage and current. An additional transistor is digitally controlled to drive up operating voltage and current upon issuance of an active command representing read, write, and/or refresh of memory. In this manner, the additional transistor provides fast compensation for fluctuations in operating voltage and current brought on by activity in the memory array.

What is claimed is: 
     
         1 . A voltage down converter for regulating an internal power supply voltage comprising:
 a first circuit configured to generate the internal power supply voltage at a voltage node in a first mode of operation; and   a second circuit configured to add load-compensating current to the voltage node in a second mode of operation.   
     
     
         2 . The voltage down converter of  claim 1 , wherein the second circuit includes an active charge injector transistor for adding the load-compensating current to the voltage node in the second mode of operation. 
     
     
         3 . The voltage down converter of  claim 2 , wherein the second mode of operation includes a read operation. 
     
     
         4 . The voltage down converter of  claim 2 , wherein the the second mode of operation includes a write operation. 
     
     
         5 . The voltage down converter of  claim 2 , wherein the second mode of operation includes a refresh operation. 
     
     
         6 . The voltage down converter of  claim 1 , wherein at least one control signal is provided in the second mode of operation, which includes a first control signal and a second control signal, the second circuit including
 a first active charge injector transistor for adding a first current to the voltage node in response to the first control signal, and   a second active charge injector transistor for adding a second current to the voltage node in response to the second control signal.   
     
     
         7 . The voltage down converter of  claim 6 , wherein the first control signal is provided in response to one of a read operation or a write operation. 
     
     
         8 . The voltage down converter of  claim 7 , wherein the second control signal is provided in response to a refresh operation. 
     
     
         9 . The voltage down converter of  claim 8 , wherein the first control signal and the second control signal are provided at substantially the same time.