Self-aligned bottom plate for metal high-k dielectric metal insulator metal (mim) embedded dynamic random access memory

Abstract

A memory device, and a method of forming a memory device, is provided that includes a capacitor with a lower electrode of a metal semiconductor alloy. In one embodiment, the memory device includes a trench present in a semiconductor substrate including a semiconductor on insulating (SOI) layer on top of a buried dielectric layer, wherein the buried dielectric layer is on top of a base semiconductor layer. A capacitor is present in the trench, wherein the capacitor includes a lower electrode of a metal semiconductor alloy having an upper edge that is self-aligned to the upper surface of the base semiconductor layer, a high-k dielectric node layer, and an upper electrode of a metal. The memory device further includes a pass transistor in electrical communication with the capacitor.

What is claimed is: 
     
         1 . A memory device comprising:
 a trench present in a semiconductor substrate including a semiconductor on insulating (SOI) layer located on an upper surface of a buried dielectric layer, wherein said buried dielectric layer is present on an upper surface of a base semiconductor layer;   a capacitor present in said trench, wherein said capacitor comprises a lower electrode comprised of a metal semiconductor alloy having an upper edge that is aligned to said upper surface of said base semiconductor layer, a high-k dielectric node layer, and an upper electrode comprised of a metal; and   a pass transistor in electrical communication with said capacitor.   
     
     
         2 . The memory device of  claim 1 , wherein metal semiconductor alloy is tungsten silicide, said high-k dielectric node layer is hafnium oxide (HfO 2 ), and said upper electrode is comprised of titanium nitride (TiN) or a mixture of TiN and doped silicon. 
     
     
         3 . The memory device of  claim 1 , wherein said base semiconductor layer has a maximum concentration of n-type, p-type or a combination of n-type and p-type dopant in sidewalls of said trench within said base semiconductor layer that is no greater than 1×10 19  atoms/cm 3 . 
     
     
         4 . The memory device of  claim 1  further comprising a void present within said trench. 
     
     
         5 . The memory device of  claim 1 , wherein said pass transistor is a field effect transistor (FET). 
     
     
         6 . The memory device of  claim 1  further comprising a dielectric spacer located within said trench and only on sidewalls of said SOI layer and said buried dielectric layer. 
     
     
         7 . The memory device of  claim 1 , wherein said trench includes a bottom portion located within said base semiconductor layer having a first width and an upper portion located within said buried dielectric layer and said SOI layer having a second width, wherein said first width is greater than said second width. 
     
     
         8 . The memory device of  claim 1 , wherein said metal semiconductor alloy includes a metal element and a semiconductor element, wherein said metal element is selected from at least one of titanium, tantalum, tungsten, platinum, palladium, hafnium, zirconium and aluminum. 
     
     
         9 . The memory device of  claim 1 , wherein said high-k dielectric node layer comprises a hafnium-containing dielectric material, aluminum oxide, silicon nitride or any combination thereof. 
     
     
         10 . The memory device of  claim 1 , wherein said metal of said upper electrode is selected from one of titanium nitride, tantalum nitride, tantalum silicon nitride, and tungsten nitride. 
     
     
         11 . The memory device of  claim 1  further comprising a trench top oxide located above said trench capacitor. 
     
     
         12 . The memory device of  claim 11 , wherein a portion of said trench top oxide is present on a portion of, but not the entirety of, said upper electrode. 
     
     
         13 . The memory device of  claim 12 , wherein a topmost surface of said trench oxide is coplanar with an upper surface of said upper electrode. 
     
     
         14 . The memory device of  claim 5 , wherein said FET includes a source region and a drain region, wherein one of said source region or said drain region directly contacts a portion of said upper electrode. 
     
     
         15 . The memory device of  claim 1 , wherein said pass transistor is located above and vertically offset from said capacitor.