Semiconductor device and semiconductor memory device

Abstract

A semiconductor device includes a plurality of memory cell arrays each including a plurality of memory cells and a first bit line coupled to the memory cells, a second bit line, a first voltage line, a plurality of first sense amplifiers each including a first transistor of which a gate is coupled to the first bit line of a corresponding one of the memory cell arrays and a second transistor, the first and second transistors in each of the first sense amplifiers being coupled in series between the second bit line and the first voltage line, a temperature detection circuit configured to detect a temperature of the semiconductor device, and a control circuit configured to receive an output of the temperature detection circuit and to supply a control signal to the gate of each of the second transistors.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a plurality of memory cell arrays each including a plurality of memory cells and a first bit line coupled to the memory cells;   a second bit line;   a first voltage line;   a plurality of first sense amplifiers each including a first transistor of which a gate is coupled to the first bit line of a corresponding one of the memory cell arrays and a second transistor, the first and second transistors in each of the first sense amplifiers being coupled in series between the second bit line and the first voltage line;   a temperature detection circuit configured to detect a temperature of the semiconductor device; and   a control circuit configured to receive an output of the temperature detection circuit and to supply a control signal to the gate of each of the second transistors.   
     
     
         2 . The semiconductor device as claimed in  claim 1 , further comprising a sense amplifier circuit including an amplifying circuit and a third transistor, the sense amplifying circuit and the third transistor being coupled in series between the second bit line and a second voltage line, the control circuit being configured to supply an additional control signal to the third transistor. 
     
     
         3 . The semiconductor device as claimed in  claim 1 , wherein each of the second transistors maintains an on-state during a first logic period of the control signal, the first logic period of the control signal being changed in response to the output of the temperature detection circuit. 
     
     
         4 . The semiconductor device as claimed in  claim 3 , wherein the output of the temperature detection circuit makes the first logic period of the control signal longer when the temperature of the semiconductor device rises. 
     
     
         5 . The semiconductor device as claimed in  claim 2 , further comprising a fourth transistor coupled between a precharge voltage line supplied with a precharge potential and the second bit line, the fourth transistor taking an on-state when at least one of the second and third transistors takes an off-state. 
     
     
         6 . The semiconductor device as claimed in  claim 1 , wherein the first and second transistors are same in conductivity type as one another. 
     
     
         7 . The semiconductor device as claimed in  claim 5 , wherein each of the memory cells includes a memory element and a fifth transistor coupled in series between a third voltage line and a corresponding one of the first bit lines, the first, second, third, and fifth transistors being same in conductivity type as one another, and the fourth transistor being different in conductivity type from each of the first, second, third, and fifth transistors. 
     
     
         8 . The semiconductor device as claimed in  claim 6 , wherein each of the first and second transistors comprises an N-conductivity type transistor. 
     
     
         9 . The semiconductor device as claimed in  claim 7 , wherein each of the first, second, third, and fifth transistors comprises an N-conductivity type transistor and the fourth transistor comprises a P-conductivity type transistor. 
     
     
         10 . The semiconductor device as claimed in  claim 1 , wherein the control circuit includes:
 a circuit node;   a gate circuit including a first input node coupled to the circuit node, a second input node and an output node coupled in common to gates of the second transistors; and   a delay circuit coupled between the circuit node and the second input node of the gate circuit, the delay circuit being configured to receive the output of the temperature detection circuit.   
     
     
         11 . The semiconductor device as claimed in  claim 10 , wherein the control circuit further includes a replica circuit replicate of the first sense amplifier circuit, the replica circuit being coupled between the circuit node and the second input node of the gate circuit in series with the delay circuit. 
     
     
         12 . The semiconductor device as claimed in  claim 2 , wherein the control circuit further includes:
 a circuit node;   an additional circuit node coupled to a gate of the third transistor; and   a delay circuit coupled between the circuit node and the additional circuit node, the delay circuit being configured to receive the output of the temperature detection circuit.   
     
     
         13 . The semiconductor device as claimed in  claim 12 , wherein the control circuit further includes a replica circuit replicate of the first sense amplifier circuit, the replica circuit being coupled between the circuit node and the additional circuit node in series with the delay circuit. 
     
     
         14 . The semiconductor device as claimed in  claim 1 , wherein the first bit line comprises a local bit line and the second bit line comprises a global bit line. 
     
     
         15 . The semiconductor device as claimed in  claim 2 , wherein the third transistor is coupled between the second bit line and the amplifying circuit. 
     
     
         16 . The semiconductor device as claimed in  claim 5 , wherein the fourth transistor takes an on-state when each of the second and third transistors takes an off-state, and takes an off-state when each of the second and third transistors takes an on-state. 
     
     
         17 . The semiconductor device as claimed in  claim 6 , further comprising a sixth transistor coupled between a second precharge voltage line supplied with a second precharge potential and the first bit line, the first, second, and sixth transistors are same in a conductivity type as each other. 
     
     
         18 . The semiconductor device as claimed in  claim 6 , wherein each of the memory cells includes a memory element and a fifth transistor coupled in series between a third voltage line and a corresponding one of the first bit lines, the first, second, and fifth transistors are same in a conductivity type as one another.